| * ASPEED AST2400 and AST2500 coprocessor interrupt controller |
| |
| This file describes the bindings for the interrupt controller present |
| in the AST2400 and AST2500 BMC SoCs which provides interrupt to the |
| ColdFire coprocessor. |
| |
| It is not a normal interrupt controller and it would be rather |
| inconvenient to create an interrupt tree for it as it somewhat shares |
| some of the same sources as the main ARM interrupt controller but with |
| different numbers. |
| |
| The AST2500 supports a SW generated interrupt |
| |
| Required properties: |
| - reg: address and length of the register for the device. |
| - compatible: "aspeed,cvic" and one of: |
| "aspeed,ast2400-cvic" |
| or |
| "aspeed,ast2500-cvic" |
| |
| - valid-sources: One cell, bitmap of supported sources for the implementation |
| |
| Optional properties; |
| - copro-sw-interrupts: List of interrupt numbers that can be used as |
| SW interrupts from the ARM to the coprocessor. |
| (AST2500 only) |
| |
| Example: |
| |
| cvic: copro-interrupt-controller@1e6c2000 { |
| compatible = "aspeed,ast2500-cvic"; |
| valid-sources = <0xffffffff>; |
| copro-sw-interrupts = <1>; |
| reg = <0x1e6c2000 0x80>; |
| }; |
