| /* |
| * Copyright 2014 Chen-Yu Tsai |
| * |
| * Chen-Yu Tsai <wens@csie.org> |
| * |
| * The code contained herein is licensed under the GNU General Public |
| * License. You may obtain a copy of the GNU General Public License |
| * Version 2 or later at the following locations: |
| * |
| * http://www.opensource.org/licenses/gpl-license.html |
| * http://www.gnu.org/copyleft/gpl.html |
| */ |
| |
| /include/ "skeleton.dtsi" |
| |
| / { |
| interrupt-parent = <&gic>; |
| |
| aliases { |
| serial0 = &uart0; |
| serial1 = &uart1; |
| serial2 = &uart2; |
| serial3 = &uart3; |
| serial4 = &uart4; |
| serial5 = &r_uart; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu@0 { |
| compatible = "arm,cortex-a7"; |
| device_type = "cpu"; |
| reg = <0>; |
| }; |
| |
| cpu@1 { |
| compatible = "arm,cortex-a7"; |
| device_type = "cpu"; |
| reg = <1>; |
| }; |
| }; |
| |
| memory { |
| reg = <0x40000000 0x40000000>; |
| }; |
| |
| clocks { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| |
| osc24M: osc24M_clk { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| clock-frequency = <24000000>; |
| clock-output-names = "osc24M"; |
| }; |
| |
| osc32k: osc32k_clk { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| clock-frequency = <32768>; |
| clock-output-names = "osc32k"; |
| }; |
| |
| pll1: clk@01c20000 { |
| #clock-cells = <0>; |
| compatible = "allwinner,sun8i-a23-pll1-clk"; |
| reg = <0x01c20000 0x4>; |
| clocks = <&osc24M>; |
| clock-output-names = "pll1"; |
| }; |
| |
| /* dummy clock until actually implemented */ |
| pll6: pll6_clk { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| clock-frequency = <600000000>; |
| clock-output-names = "pll6"; |
| }; |
| |
| cpu: cpu_clk@01c20050 { |
| #clock-cells = <0>; |
| compatible = "allwinner,sun4i-a10-cpu-clk"; |
| reg = <0x01c20050 0x4>; |
| |
| /* |
| * PLL1 is listed twice here. |
| * While it looks suspicious, it's actually documented |
| * that way both in the datasheet and in the code from |
| * Allwinner. |
| */ |
| clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>; |
| clock-output-names = "cpu"; |
| }; |
| |
| axi: axi_clk@01c20050 { |
| #clock-cells = <0>; |
| compatible = "allwinner,sun8i-a23-axi-clk"; |
| reg = <0x01c20050 0x4>; |
| clocks = <&cpu>; |
| clock-output-names = "axi"; |
| }; |
| |
| ahb1_mux: ahb1_mux_clk@01c20054 { |
| #clock-cells = <0>; |
| compatible = "allwinner,sun6i-a31-ahb1-mux-clk"; |
| reg = <0x01c20054 0x4>; |
| clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>; |
| clock-output-names = "ahb1_mux"; |
| }; |
| |
| ahb1: ahb1_clk@01c20054 { |
| #clock-cells = <0>; |
| compatible = "allwinner,sun4i-a10-ahb-clk"; |
| reg = <0x01c20054 0x4>; |
| clocks = <&ahb1_mux>; |
| clock-output-names = "ahb1"; |
| }; |
| |
| apb1: apb1_clk@01c20054 { |
| #clock-cells = <0>; |
| compatible = "allwinner,sun4i-a10-apb0-clk"; |
| reg = <0x01c20054 0x4>; |
| clocks = <&ahb1>; |
| clock-output-names = "apb1"; |
| }; |
| |
| ahb1_gates: clk@01c20060 { |
| #clock-cells = <1>; |
| compatible = "allwinner,sun8i-a23-ahb1-gates-clk"; |
| reg = <0x01c20060 0x8>; |
| clocks = <&ahb1>; |
| clock-output-names = "ahb1_mipidsi", "ahb1_dma", |
| "ahb1_mmc0", "ahb1_mmc1", "ahb1_mmc2", |
| "ahb1_nand", "ahb1_sdram", |
| "ahb1_hstimer", "ahb1_spi0", |
| "ahb1_spi1", "ahb1_otg", "ahb1_ehci", |
| "ahb1_ohci", "ahb1_ve", "ahb1_lcd", |
| "ahb1_csi", "ahb1_be", "ahb1_fe", |
| "ahb1_gpu", "ahb1_spinlock", |
| "ahb1_drc"; |
| }; |
| |
| apb1_gates: clk@01c20068 { |
| #clock-cells = <1>; |
| compatible = "allwinner,sun8i-a23-apb1-gates-clk"; |
| reg = <0x01c20068 0x4>; |
| clocks = <&apb1>; |
| clock-output-names = "apb1_codec", "apb1_pio", |
| "apb1_daudio0", "apb1_daudio1"; |
| }; |
| |
| apb2_mux: apb2_mux_clk@01c20058 { |
| #clock-cells = <0>; |
| compatible = "allwinner,sun4i-a10-apb1-mux-clk"; |
| reg = <0x01c20058 0x4>; |
| clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>; |
| clock-output-names = "apb2_mux"; |
| }; |
| |
| apb2: apb2_clk@01c20058 { |
| #clock-cells = <0>; |
| compatible = "allwinner,sun6i-a31-apb2-div-clk"; |
| reg = <0x01c20058 0x4>; |
| clocks = <&apb2_mux>; |
| clock-output-names = "apb2"; |
| }; |
| |
| apb2_gates: clk@01c2006c { |
| #clock-cells = <1>; |
| compatible = "allwinner,sun8i-a23-apb2-gates-clk"; |
| reg = <0x01c2006c 0x4>; |
| clocks = <&apb2>; |
| clock-output-names = "apb2_i2c0", "apb2_i2c1", |
| "apb2_i2c2", "apb2_uart0", |
| "apb2_uart1", "apb2_uart2", |
| "apb2_uart3", "apb2_uart4"; |
| }; |
| }; |
| |
| soc@01c00000 { |
| compatible = "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| |
| ahb1_rst: reset@01c202c0 { |
| #reset-cells = <1>; |
| compatible = "allwinner,sun6i-a31-clock-reset"; |
| reg = <0x01c202c0 0xc>; |
| }; |
| |
| apb1_rst: reset@01c202d0 { |
| #reset-cells = <1>; |
| compatible = "allwinner,sun6i-a31-clock-reset"; |
| reg = <0x01c202d0 0x4>; |
| }; |
| |
| apb2_rst: reset@01c202d8 { |
| #reset-cells = <1>; |
| compatible = "allwinner,sun6i-a31-clock-reset"; |
| reg = <0x01c202d8 0x4>; |
| }; |
| |
| timer@01c20c00 { |
| compatible = "allwinner,sun4i-a10-timer"; |
| reg = <0x01c20c00 0xa0>; |
| interrupts = <0 18 4>, |
| <0 19 4>; |
| clocks = <&osc24M>; |
| }; |
| |
| wdt0: watchdog@01c20ca0 { |
| compatible = "allwinner,sun6i-a31-wdt"; |
| reg = <0x01c20ca0 0x20>; |
| interrupts = <0 25 4>; |
| }; |
| |
| uart0: serial@01c28000 { |
| compatible = "snps,dw-apb-uart"; |
| reg = <0x01c28000 0x400>; |
| interrupts = <0 0 4>; |
| reg-shift = <2>; |
| reg-io-width = <4>; |
| clocks = <&apb2_gates 16>; |
| resets = <&apb2_rst 16>; |
| status = "disabled"; |
| }; |
| |
| uart1: serial@01c28400 { |
| compatible = "snps,dw-apb-uart"; |
| reg = <0x01c28400 0x400>; |
| interrupts = <0 1 4>; |
| reg-shift = <2>; |
| reg-io-width = <4>; |
| clocks = <&apb2_gates 17>; |
| resets = <&apb2_rst 17>; |
| status = "disabled"; |
| }; |
| |
| uart2: serial@01c28800 { |
| compatible = "snps,dw-apb-uart"; |
| reg = <0x01c28800 0x400>; |
| interrupts = <0 2 4>; |
| reg-shift = <2>; |
| reg-io-width = <4>; |
| clocks = <&apb2_gates 18>; |
| resets = <&apb2_rst 18>; |
| status = "disabled"; |
| }; |
| |
| uart3: serial@01c28c00 { |
| compatible = "snps,dw-apb-uart"; |
| reg = <0x01c28c00 0x400>; |
| interrupts = <0 3 4>; |
| reg-shift = <2>; |
| reg-io-width = <4>; |
| clocks = <&apb2_gates 19>; |
| resets = <&apb2_rst 19>; |
| status = "disabled"; |
| }; |
| |
| uart4: serial@01c29000 { |
| compatible = "snps,dw-apb-uart"; |
| reg = <0x01c29000 0x400>; |
| interrupts = <0 4 4>; |
| reg-shift = <2>; |
| reg-io-width = <4>; |
| clocks = <&apb2_gates 20>; |
| resets = <&apb2_rst 20>; |
| status = "disabled"; |
| }; |
| |
| gic: interrupt-controller@01c81000 { |
| compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; |
| reg = <0x01c81000 0x1000>, |
| <0x01c82000 0x1000>, |
| <0x01c84000 0x2000>, |
| <0x01c86000 0x2000>; |
| interrupt-controller; |
| #interrupt-cells = <3>; |
| interrupts = <1 9 0xf04>; |
| }; |
| |
| prcm@01f01400 { |
| compatible = "allwinner,sun8i-a23-prcm"; |
| reg = <0x01f01400 0x200>; |
| |
| ar100: ar100_clk { |
| compatible = "fixed-factor-clock"; |
| #clock-cells = <0>; |
| clock-div = <1>; |
| clock-mult = <1>; |
| clocks = <&osc24M>; |
| clock-output-names = "ar100"; |
| }; |
| |
| ahb0: ahb0_clk { |
| compatible = "fixed-factor-clock"; |
| #clock-cells = <0>; |
| clock-div = <1>; |
| clock-mult = <1>; |
| clocks = <&ar100>; |
| clock-output-names = "ahb0"; |
| }; |
| |
| apb0: apb0_clk { |
| compatible = "allwinner,sun8i-a23-apb0-clk"; |
| #clock-cells = <0>; |
| clocks = <&ahb0>; |
| clock-output-names = "apb0"; |
| }; |
| |
| apb0_gates: apb0_gates_clk { |
| compatible = "allwinner,sun8i-a23-apb0-gates-clk"; |
| #clock-cells = <1>; |
| clocks = <&apb0>; |
| clock-output-names = "apb0_pio", "apb0_timer", |
| "apb0_rsb", "apb0_uart", |
| "apb0_i2c"; |
| }; |
| |
| apb0_rst: apb0_rst { |
| compatible = "allwinner,sun6i-a31-clock-reset"; |
| #reset-cells = <1>; |
| }; |
| }; |
| |
| r_uart: serial@01f02800 { |
| compatible = "snps,dw-apb-uart"; |
| reg = <0x01f02800 0x400>; |
| interrupts = <0 38 4>; |
| reg-shift = <2>; |
| reg-io-width = <4>; |
| clocks = <&apb0_gates 4>; |
| resets = <&apb0_rst 4>; |
| status = "disabled"; |
| }; |
| }; |
| }; |
