| * NVIDIA Tegra APB DMA controller |
| - compatible: Should be "nvidia,<chip>-apbdma" |
| - reg: Should contain DMA registers location and length. This shuld include |
| all of the per-channel registers. |
| - interrupts: Should contain all of the per-channel DMA interrupts. |
| - clocks: Must contain one entry, for the module clock. |
| See ../clocks/clock-bindings.txt for details. |
| - resets : Must contain an entry for each entry in reset-names. |
| See ../reset/reset.txt for details. |
| - reset-names : Must include the following entries: |
| - #dma-cells : Must be <1>. This dictates the length of DMA specifiers in |
| client nodes' dmas properties. The specifier represents the DMA request |
| select value for the peripheral. For more details, consult the Tegra TRM's |
| documentation of the APB DMA channel control register REQ_SEL field. |
| compatible = "nvidia,tegra20-apbdma"; |
| reg = <0x6000a000 0x1200>; |
| interrupts = < 0 136 0x04 |
| clocks = <&tegra_car 34>; |
| resets = <&tegra_car 34>; |