arch/arm64/boot/dts/qcom/sm8450.dtsi

// SPDX-License-Identifier: BSD-3-Clause
/*
 * Copyright (c) 2021, Linaro Limited
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-sm8450.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>

/ {
	interrupt-parent = <&intc>;

	#address-cells = <2>;
	#size-cells = <2>;

	chosen { };

	clocks {
		xo_board: xo-board {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <76800000>;
		};

		sleep_clk: sleep-clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32000>;
		};
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		CPU0: cpu@0 {
			device_type = "cpu";
			compatible = "qcom,kryo780";
			reg = <0x0 0x0>;
			enable-method = "psci";
			next-level-cache = <&L2_0>;
			power-domains = <&CPU_PD0>;
			power-domain-names = "psci";
			qcom,freq-domain = <&cpufreq_hw 0>;
			L2_0: l2-cache {
			      compatible = "cache";
			      next-level-cache = <&L3_0>;
				L3_0: l3-cache {
				      compatible = "cache";
				};
			};
		};

		CPU1: cpu@100 {
			device_type = "cpu";
			compatible = "qcom,kryo780";
			reg = <0x0 0x100>;
			enable-method = "psci";
			next-level-cache = <&L2_100>;
			power-domains = <&CPU_PD1>;
			power-domain-names = "psci";
			qcom,freq-domain = <&cpufreq_hw 0>;
			L2_100: l2-cache {
			      compatible = "cache";
			      next-level-cache = <&L3_0>;
			};
		};

		CPU2: cpu@200 {
			device_type = "cpu";
			compatible = "qcom,kryo780";
			reg = <0x0 0x200>;
			enable-method = "psci";
			next-level-cache = <&L2_200>;
			power-domains = <&CPU_PD2>;
			power-domain-names = "psci";
			qcom,freq-domain = <&cpufreq_hw 0>;
			L2_200: l2-cache {
			      compatible = "cache";
			      next-level-cache = <&L3_0>;
			};
		};

		CPU3: cpu@300 {
			device_type = "cpu";
			compatible = "qcom,kryo780";
			reg = <0x0 0x300>;
			enable-method = "psci";
			next-level-cache = <&L2_300>;
			power-domains = <&CPU_PD3>;
			power-domain-names = "psci";
			qcom,freq-domain = <&cpufreq_hw 0>;
			L2_300: l2-cache {
			      compatible = "cache";
			      next-level-cache = <&L3_0>;
			};
		};

		CPU4: cpu@400 {
			device_type = "cpu";
			compatible = "qcom,kryo780";
			reg = <0x0 0x400>;
			enable-method = "psci";
			next-level-cache = <&L2_400>;
			power-domains = <&CPU_PD4>;
			power-domain-names = "psci";
			qcom,freq-domain = <&cpufreq_hw 1>;
			L2_400: l2-cache {
			      compatible = "cache";
			      next-level-cache = <&L3_0>;
			};
		};

		CPU5: cpu@500 {
			device_type = "cpu";
			compatible = "qcom,kryo780";
			reg = <0x0 0x500>;
			enable-method = "psci";
			next-level-cache = <&L2_500>;
			power-domains = <&CPU_PD5>;
			power-domain-names = "psci";
			qcom,freq-domain = <&cpufreq_hw 1>;
			L2_500: l2-cache {
			      compatible = "cache";
			      next-level-cache = <&L3_0>;
			};

		};

		CPU6: cpu@600 {
			device_type = "cpu";
			compatible = "qcom,kryo780";
			reg = <0x0 0x600>;
			enable-method = "psci";
			next-level-cache = <&L2_600>;
			power-domains = <&CPU_PD6>;
			power-domain-names = "psci";
			qcom,freq-domain = <&cpufreq_hw 1>;
			L2_600: l2-cache {
			      compatible = "cache";
			      next-level-cache = <&L3_0>;
			};
		};

		CPU7: cpu@700 {
			device_type = "cpu";
			compatible = "qcom,kryo780";
			reg = <0x0 0x700>;
			enable-method = "psci";
			next-level-cache = <&L2_700>;
			power-domains = <&CPU_PD7>;
			power-domain-names = "psci";
			qcom,freq-domain = <&cpufreq_hw 2>;
			L2_700: l2-cache {
			      compatible = "cache";
			      next-level-cache = <&L3_0>;
			};
		};

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&CPU0>;
				};

				core1 {
					cpu = <&CPU1>;
				};

				core2 {
					cpu = <&CPU2>;
				};

				core3 {
					cpu = <&CPU3>;
				};

				core4 {
					cpu = <&CPU4>;
				};

				core5 {
					cpu = <&CPU5>;
				};

				core6 {
					cpu = <&CPU6>;
				};

				core7 {
					cpu = <&CPU7>;
				};
			};
		};

		idle-states {
			entry-method = "psci";

			LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
				compatible = "arm,idle-state";
				idle-state-name = "silver-rail-power-collapse";
				arm,psci-suspend-param = <0x40000004>;
				entry-latency-us = <274>;
				exit-latency-us = <480>;
				min-residency-us = <3934>;
				local-timer-stop;
			};

			BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
				compatible = "arm,idle-state";
				idle-state-name = "gold-rail-power-collapse";
				arm,psci-suspend-param = <0x40000004>;
				entry-latency-us = <327>;
				exit-latency-us = <1502>;
				min-residency-us = <4488>;
				local-timer-stop;
			};
		};

		domain-idle-states {
			CLUSTER_SLEEP_0: cluster-sleep-0 {
				compatible = "domain-idle-state";
				idle-state-name = "cluster-l3-off";
				arm,psci-suspend-param = <0x4100c344>;
				entry-latency-us = <584>;
				exit-latency-us = <2332>;
				min-residency-us = <6118>;
				local-timer-stop;
			};

			CLUSTER_SLEEP_1: cluster-sleep-1 {
				compatible = "domain-idle-state";
				idle-state-name = "cluster-power-collapse";
				arm,psci-suspend-param = <0x4100c344>;
				entry-latency-us = <2893>;
				exit-latency-us = <4023>;
				min-residency-us = <9987>;
				local-timer-stop;
			};
		};
	};

	firmware {
		scm: scm {
			compatible = "qcom,scm-sm8450", "qcom,scm";
			#reset-cells = <1>;
		};
	};

	memory@a0000000 {
		device_type = "memory";
		/* We expect the bootloader to fill in the size */
		reg = <0x0 0xa0000000 0x0 0x0>;
	};

	pmu {
		compatible = "arm,armv8-pmuv3";
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";

		CPU_PD0: cpu0 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
		};

		CPU_PD1: cpu1 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
		};

		CPU_PD2: cpu2 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
		};

		CPU_PD3: cpu3 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
		};

		CPU_PD4: cpu4 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
			domain-idle-states = <&BIG_CPU_SLEEP_0>;
		};

		CPU_PD5: cpu5 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
			domain-idle-states = <&BIG_CPU_SLEEP_0>;
		};

		CPU_PD6: cpu6 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
			domain-idle-states = <&BIG_CPU_SLEEP_0>;
		};

		CPU_PD7: cpu7 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
			domain-idle-states = <&BIG_CPU_SLEEP_0>;
		};

		CLUSTER_PD: cpu-cluster0 {
			#power-domain-cells = <0>;
			domain-idle-states = <&CLUSTER_SLEEP_0>;
		};
	};

	reserved_memory: reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		hyp_mem: memory@80000000 {
			reg = <0x0 0x80000000 0x0 0x600000>;
			no-map;
		};

		xbl_dt_log_mem: memory@80600000 {
			reg = <0x0 0x80600000 0x0 0x40000>;
			no-map;
		};

		xbl_ramdump_mem: memory@80640000 {
			reg = <0x0 0x80640000 0x0 0x180000>;
			no-map;
		};

		xbl_sc_mem: memory@807c0000 {
			reg = <0x0 0x807c0000 0x0 0x40000>;
			no-map;
		};

		aop_image_mem: memory@80800000 {
			reg = <0x0 0x80800000 0x0 0x60000>;
			no-map;
		};

		aop_cmd_db_mem: memory@80860000 {
			compatible = "qcom,cmd-db";
			reg = <0x0 0x80860000 0x0 0x20000>;
			no-map;
		};

		aop_config_mem: memory@80880000 {
			reg = <0x0 0x80880000 0x0 0x20000>;
			no-map;
		};

		tme_crash_dump_mem: memory@808a0000 {
			reg = <0x0 0x808a0000 0x0 0x40000>;
			no-map;
		};

		tme_log_mem: memory@808e0000 {
			reg = <0x0 0x808e0000 0x0 0x4000>;
			no-map;
		};

		uefi_log_mem: memory@808e4000 {
			reg = <0x0 0x808e4000 0x0 0x10000>;
			no-map;
		};

		/* secdata region can be reused by apps */
		smem: memory@80900000 {
			compatible = "qcom,smem";
			reg = <0x0 0x80900000 0x0 0x200000>;
			hwlocks = <&tcsr_mutex 3>;
			no-map;
		};

		cpucp_fw_mem: memory@80b00000 {
			reg = <0x0 0x80b00000 0x0 0x100000>;
			no-map;
		};

		cdsp_secure_heap: memory@80c00000 {
			reg = <0x0 0x80c00000 0x0 0x4600000>;
			no-map;
		};

		camera_mem: memory@85200000 {
			reg = <0x0 0x85200000 0x0 0x500000>;
			no-map;
		};

		video_mem: memory@85700000 {
			reg = <0x0 0x85700000 0x0 0x700000>;
			no-map;
		};

		adsp_mem: memory@85e00000 {
			reg = <0x0 0x85e00000 0x0 0x2100000>;
			no-map;
		};

		slpi_mem: memory@88000000 {
			reg = <0x0 0x88000000 0x0 0x1900000>;
			no-map;
		};

		cdsp_mem: memory@89900000 {
			reg = <0x0 0x89900000 0x0 0x2000000>;
			no-map;
		};

		ipa_fw_mem: memory@8b900000 {
			reg = <0x0 0x8b900000 0x0 0x10000>;
			no-map;
		};

		ipa_gsi_mem: memory@8b910000 {
			reg = <0x0 0x8b910000 0x0 0xa000>;
			no-map;
		};

		gpu_micro_code_mem: memory@8b91a000 {
			reg = <0x0 0x8b91a000 0x0 0x2000>;
			no-map;
		};

		spss_region_mem: memory@8ba00000 {
			reg = <0x0 0x8ba00000 0x0 0x180000>;
			no-map;
		};

		/* First part of the "SPU secure shared memory" region */
		spu_tz_shared_mem: memory@8bb80000 {
			reg = <0x0 0x8bb80000 0x0 0x60000>;
			no-map;
		};

		/* Second part of the "SPU secure shared memory" region */
		spu_modem_shared_mem: memory@8bbe0000 {
			reg = <0x0 0x8bbe0000 0x0 0x20000>;
			no-map;
		};

		mpss_mem: memory@8bc00000 {
			reg = <0x0 0x8bc00000 0x0 0x13200000>;
			no-map;
		};

		cvp_mem: memory@9ee00000 {
			reg = <0x0 0x9ee00000 0x0 0x700000>;
			no-map;
		};

		global_sync_mem: memory@a6f00000 {
			reg = <0x0 0xa6f00000 0x0 0x100000>;
			no-map;
		};

		/* uefi region can be reused by APPS */

		/* Linux kernel image is loaded at 0xa0000000 */

		oem_vm_mem: memory@bb000000 {
			reg = <0x0 0xbb000000 0x0 0x5000000>;
			no-map;
		};

		mte_mem: memory@c0000000 {
			reg = <0x0 0xc0000000 0x0 0x20000000>;
			no-map;
		};

		qheebsp_reserved_mem: memory@e0000000 {
			reg = <0x0 0xe0000000 0x0 0x600000>;
			no-map;
		};

		cpusys_vm_mem: memory@e0600000 {
			reg = <0x0 0xe0600000 0x0 0x400000>;
			no-map;
		};

		hyp_reserved_mem: memory@e0a00000 {
			reg = <0x0 0xe0a00000 0x0 0x100000>;
			no-map;
		};

		trust_ui_vm_mem: memory@e0b00000 {
			reg = <0x0 0xe0b00000 0x0 0x4af3000>;
			no-map;
		};

		trust_ui_vm_qrtr: memory@e55f3000 {
			reg = <0x0 0xe55f3000 0x0 0x9000>;
			no-map;
		};

		trust_ui_vm_vblk0_ring: memory@e55fc000 {
			reg = <0x0 0xe55fc000 0x0 0x4000>;
			no-map;
		};

		trust_ui_vm_swiotlb: memory@e5600000 {
			reg = <0x0 0xe5600000 0x0 0x100000>;
			no-map;
		};

		tz_stat_mem: memory@e8800000 {
			reg = <0x0 0xe8800000 0x0 0x100000>;
			no-map;
		};

		tags_mem: memory@e8900000 {
			reg = <0x0 0xe8900000 0x0 0x1200000>;
			no-map;
		};

		qtee_mem: memory@e9b00000 {
			reg = <0x0 0xe9b00000 0x0 0x500000>;
			no-map;
		};

		trusted_apps_mem: memory@ea000000 {
			reg = <0x0 0xea000000 0x0 0x3900000>;
			no-map;
		};

		trusted_apps_ext_mem: memory@ed900000 {
			reg = <0x0 0xed900000 0x0 0x3b00000>;
			no-map;
		};
	};

	soc: soc@0 {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges = <0 0 0 0 0x10 0>;
		dma-ranges = <0 0 0 0 0x10 0>;
		compatible = "simple-bus";

		gcc: clock-controller@100000 {
			compatible = "qcom,gcc-sm8450";
			reg = <0x0 0x00100000 0x0 0x1f4200>;
			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;
			clock-names = "bi_tcxo", "sleep_clk";
			clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
		};

		qupv3_id_0: geniqup@9c0000 {
			compatible = "qcom,geni-se-qup";
			reg = <0x0 0x009c0000 0x0 0x2000>;
			clock-names = "m-ahb", "s-ahb";
			clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
				 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
			#address-cells = <2>;
			#size-cells = <2>;
			ranges;
			status = "disabled";

			uart7: serial@99c000 {
				compatible = "qcom,geni-debug-uart";
				reg = <0 0x0099c000 0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
				interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};
		};

		qupv3_id_1: geniqup@ac0000 {
			compatible = "qcom,geni-se-qup";
			reg = <0x0 0x00ac0000 0x0 0x6000>;
			clock-names = "m-ahb", "s-ahb";
			clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
				 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
			#address-cells = <2>;
			#size-cells = <2>;
			ranges;
			status = "disabled";

			i2c13: i2c@a94000 {
				compatible = "qcom,geni-i2c";
				reg = <0 0x00a94000 0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_i2c13_data_clk>;
				interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			i2c14: i2c@a98000 {
				compatible = "qcom,geni-i2c";
				reg = <0 0x00a98000 0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_i2c14_data_clk>;
				interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};
		};

		tcsr_mutex: hwlock@1f40000 {
			compatible = "qcom,tcsr-mutex";
			reg = <0x0 0x01f40000 0x0 0x40000>;
			#hwlock-cells = <1>;
		};

		usb_1_hsphy: phy@88e3000 {
			compatible = "qcom,sm8450-usb-hs-phy",
				     "qcom,usb-snps-hs-7nm-phy";
			reg = <0 0x088e3000 0 0x400>;
			status = "disabled";
			#phy-cells = <0>;

			clocks = <&rpmhcc RPMH_CXO_CLK>;
			clock-names = "ref";

			resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
		};

		usb_1_qmpphy: phy-wrapper@88e9000 {
			compatible = "qcom,sm8450-qmp-usb3-phy";
			reg = <0 0x088e9000 0 0x200>,
			      <0 0x088e8000 0 0x20>;
			status = "disabled";
			#address-cells = <2>;
			#size-cells = <2>;
			ranges;

			clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
				 <&rpmhcc RPMH_CXO_CLK>,
				 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
			clock-names = "aux", "ref_clk_src", "com_aux";

			resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
				 <&gcc GCC_USB3_PHY_PRIM_BCR>;
			reset-names = "phy", "common";

			usb_1_ssphy: phy@88e9200 {
				reg = <0 0x088e9200 0 0x200>,
				      <0 0x088e9400 0 0x200>,
				      <0 0x088e9c00 0 0x400>,
				      <0 0x088e9600 0 0x200>,
				      <0 0x088e9800 0 0x200>,
				      <0 0x088e9a00 0 0x100>;
				#phy-cells = <0>;
				#clock-cells = <1>;
				clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
				clock-names = "pipe0";
				clock-output-names = "usb3_phy_pipe_clk_src";
			};
		};

		pdc: interrupt-controller@b220000 {
			compatible = "qcom,sm8450-pdc", "qcom,pdc";
			reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
			qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>,
					  <94 609 31>, <125 63 1>, <126 716 12>;
			#interrupt-cells = <2>;
			interrupt-parent = <&intc>;
			interrupt-controller;
		};

		tlmm: pinctrl@f100000 {
			compatible = "qcom,sm8450-tlmm";
			reg = <0 0x0f100000 0 0x300000>;
			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			gpio-ranges = <&tlmm 0 0 211>;
			wakeup-parent = <&pdc>;

			qup_i2c13_data_clk: qup-i2c13-data-clk {
				pins = "gpio48", "gpio49";
				function = "qup13";
				drive-strength = <2>;
				bias-pull-up;
			};

			qup_i2c14_data_clk: qup-i2c14-data-clk {
				pins = "gpio52", "gpio53";
				function = "qup14";
				drive-strength = <2>;
				bias-pull-up;
			};

			qup_uart7_rx: qup-uart7-rx {
				pins = "gpio26";
				function = "qup7";
				drive-strength = <2>;
				bias-disable;
			};

			qup_uart7_tx: qup-uart7-tx {
				pins = "gpio27";
				function = "qup7";
				drive-strength = <2>;
				bias-disable;
			};
		};

		apps_smmu: iommu@15000000 {
			compatible = "qcom,sm8450-smmu-500", "arm,mmu-500";
			reg = <0 0x15000000 0 0x100000>;
			#iommu-cells = <2>;
			#global-interrupts = <2>;
			interrupts =    <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>;
		};

		intc: interrupt-controller@17100000 {
			compatible = "arm,gic-v3";
			#interrupt-cells = <3>;
			interrupt-controller;
			#redistributor-regions = <1>;
			redistributor-stride = <0x0 0x40000>;
			reg = <0x0 0x17100000 0x0 0x10000>,     /* GICD */
			      <0x0 0x17180000 0x0 0x200000>;    /* GICR * 8 */
			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
		};

		timer@17420000 {
			compatible = "arm,armv7-timer-mem";
			#address-cells = <2>;
			#size-cells = <2>;
			ranges;
			reg = <0x0 0x17420000 0x0 0x1000>;
			clock-frequency = <19200000>;

			frame@17421000 {
				frame-number = <0>;
				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x0 0x17421000 0x0 0x1000>,
				      <0x0 0x17422000 0x0 0x1000>;
			};

			frame@17423000 {
				frame-number = <1>;
				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x0 0x17423000 0x0 0x1000>;
				status = "disabled";
			};

			frame@17425000 {
				frame-number = <2>;
				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x0 0x17425000 0x0 0x1000>;
				status = "disabled";
			};

			frame@17427000 {
				frame-number = <3>;
				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x0 0x17427000 0x0 0x1000>;
				status = "disabled";
			};

			frame@17429000 {
				frame-number = <4>;
				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x0 0x17429000 0x0 0x1000>;
				status = "disabled";
			};

			frame@1742b000 {
				frame-number = <5>;
				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x0 0x1742b000 0x0 0x1000>;
				status = "disabled";
			};

			frame@1742d000 {
				frame-number = <6>;
				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x0 0x1742d000 0x0 0x1000>;
				status = "disabled";
			};
		};

		apps_rsc: rsc@17a00000 {
			label = "apps_rsc";
			compatible = "qcom,rpmh-rsc";
			reg = <0x0 0x17a00000 0x0 0x10000>,
			      <0x0 0x17a10000 0x0 0x10000>,
			      <0x0 0x17a20000 0x0 0x10000>,
			      <0x0 0x17a30000 0x0 0x10000>;
			reg-names = "drv-0", "drv-1", "drv-2", "drv-3";
			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
			qcom,tcs-offset = <0xd00>;
			qcom,drv-id = <2>;
			qcom,tcs-config = <ACTIVE_TCS  3>, <SLEEP_TCS   2>,
					  <WAKE_TCS    2>, <CONTROL_TCS 0>;

			apps_bcm_voter: bcm-voter {
				compatible = "qcom,bcm-voter";
			};

			rpmhcc: clock-controller {
				compatible = "qcom,sm8450-rpmh-clk";
				#clock-cells = <1>;
				clock-names = "xo";
				clocks = <&xo_board>;
			};

			rpmhpd: power-controller {
				compatible = "qcom,sm8450-rpmhpd";
				#power-domain-cells = <1>;
				operating-points-v2 = <&rpmhpd_opp_table>;

				rpmhpd_opp_table: opp-table {
					compatible = "operating-points-v2";

					rpmhpd_opp_ret: opp1 {
						opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
					};

					rpmhpd_opp_min_svs: opp2 {
						opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
					};

					rpmhpd_opp_low_svs: opp3 {
						opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
					};

					rpmhpd_opp_svs: opp4 {
						opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
					};

					rpmhpd_opp_svs_l1: opp5 {
						opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
					};

					rpmhpd_opp_nom: opp6 {
						opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
					};

					rpmhpd_opp_nom_l1: opp7 {
						opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
					};

					rpmhpd_opp_nom_l2: opp8 {
						opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
					};

					rpmhpd_opp_turbo: opp9 {
						opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
					};

					rpmhpd_opp_turbo_l1: opp10 {
						opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
					};
				};
			};
		};

		cpufreq_hw: cpufreq@17d91000 {
			compatible = "qcom,sm8450-cpufreq-epss", "qcom,cpufreq-epss";
			reg = <0 0x17d91000 0 0x1000>,
			      <0 0x17d92000 0 0x1000>,
			      <0 0x17d93000 0 0x1000>;
			reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
			clock-names = "xo", "alternate";
			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
			#freq-domain-cells = <1>;
		};

		ufs_mem_hc: ufshc@1d84000 {
			compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
				     "jedec,ufs-2.0";
			reg = <0 0x01d84000 0 0x3000>;
			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
			phys = <&ufs_mem_phy_lanes>;
			phy-names = "ufsphy";
			lanes-per-direction = <2>;
			#reset-cells = <1>;
			resets = <&gcc GCC_UFS_PHY_BCR>;
			reset-names = "rst";

			power-domains = <&gcc UFS_PHY_GDSC>;

			iommus = <&apps_smmu 0xe0 0x0>;

			clock-names =
				"core_clk",
				"bus_aggr_clk",
				"iface_clk",
				"core_clk_unipro",
				"ref_clk",
				"tx_lane0_sync_clk",
				"rx_lane0_sync_clk",
				"rx_lane1_sync_clk";
			clocks =
				<&gcc GCC_UFS_PHY_AXI_CLK>,
				<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
				<&gcc GCC_UFS_PHY_AHB_CLK>,
				<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
				<&rpmhcc RPMH_CXO_CLK>,
				<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
				<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
				<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
			freq-table-hz =
				<75000000 300000000>,
				<0 0>,
				<0 0>,
				<75000000 300000000>,
				<75000000 300000000>,
				<0 0>,
				<0 0>,
				<0 0>;
			status = "disabled";
		};

		ufs_mem_phy: phy@1d87000 {
			compatible = "qcom,sm8450-qmp-ufs-phy";
			reg = <0 0x01d87000 0 0xe10>;
			#address-cells = <2>;
			#size-cells = <2>;
			ranges;
			clock-names = "ref", "ref_aux", "qref";
			clocks = <&rpmhcc RPMH_CXO_CLK>,
				 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
				 <&gcc GCC_UFS_0_CLKREF_EN>;

			resets = <&ufs_mem_hc 0>;
			reset-names = "ufsphy";
			status = "disabled";

			ufs_mem_phy_lanes: lanes@1d87400 {
				reg = <0 0x01d87400 0 0x108>,
				      <0 0x01d87600 0 0x1e0>,
				      <0 0x01d87c00 0 0x1dc>,
				      <0 0x01d87800 0 0x108>,
				      <0 0x01d87a00 0 0x1e0>;
				#phy-cells = <0>;
				#clock-cells = <0>;
			};
		};

		usb_1: usb@a6f8800 {
			compatible = "qcom,sm8450-dwc3", "qcom,dwc3";
			reg = <0 0x0a6f8800 0 0x400>;
			status = "disabled";
			#address-cells = <2>;
			#size-cells = <2>;
			ranges;

			clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
				 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
				 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
				 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
				 <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
			clock-names = "cfg_noc", "core", "iface", "mock_utmi",
				      "sleep";

			assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
					  <&gcc GCC_USB30_PRIM_MASTER_CLK>;
			assigned-clock-rates = <19200000>, <200000000>;

			interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
					      <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
					      <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
					      <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
					  "dm_hs_phy_irq", "ss_phy_irq";

			power-domains = <&gcc USB30_PRIM_GDSC>;

			resets = <&gcc GCC_USB30_PRIM_BCR>;

			usb_1_dwc3: usb@a600000 {
				compatible = "snps,dwc3";
				reg = <0 0x0a600000 0 0xcd00>;
				interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
				iommus = <&apps_smmu 0x0 0x0>;
				snps,dis_u2_susphy_quirk;
				snps,dis_enblslpm_quirk;
				phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
				phy-names = "usb2-phy", "usb3-phy";
			};
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
		clock-frequency = <19200000>;
	};
};