| # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| %YAML 1.2 |
| --- |
| $id: http://devicetree.org/schemas/mailbox/fsl,mu.yaml# |
| $schema: http://devicetree.org/meta-schemas/core.yaml# |
| |
| title: NXP i.MX Messaging Unit (MU) |
| |
| maintainers: |
| - Dong Aisheng <aisheng.dong@nxp.com> |
| |
| description: | |
| The Messaging Unit module enables two processors within the SoC to |
| communicate and coordinate by passing messages (e.g. data, status |
| and control) through the MU interface. The MU also provides the ability |
| for one processor to signal the other processor using interrupts. |
| |
| Because the MU manages the messaging between processors, the MU uses |
| different clocks (from each side of the different peripheral buses). |
| Therefore, the MU must synchronize the accesses from one side to the |
| other. The MU accomplishes synchronization using two sets of matching |
| registers (Processor A-facing, Processor B-facing). |
| |
| properties: |
| compatible: |
| oneOf: |
| - const: fsl,imx6sx-mu |
| - const: fsl,imx7ulp-mu |
| - const: fsl,imx8ulp-mu |
| - const: fsl,imx8-mu-scu |
| - const: fsl,imx8ulp-mu-s4 |
| - items: |
| - enum: |
| - fsl,imx7s-mu |
| - fsl,imx8mq-mu |
| - fsl,imx8mm-mu |
| - fsl,imx8mn-mu |
| - fsl,imx8mp-mu |
| - fsl,imx8qm-mu |
| - fsl,imx8qxp-mu |
| - const: fsl,imx6sx-mu |
| - description: To communicate with i.MX8 SCU with fast IPC |
| items: |
| - const: fsl,imx8-mu-scu |
| - enum: |
| - fsl,imx8qm-mu |
| - fsl,imx8qxp-mu |
| - const: fsl,imx6sx-mu |
| |
| reg: |
| maxItems: 1 |
| |
| interrupts: |
| maxItems: 1 |
| |
| "#mbox-cells": |
| description: | |
| <&phandle type channel> |
| phandle : Label name of controller |
| type : Channel type |
| channel : Channel number |
| |
| This MU support 4 type of unidirectional channels, each type |
| has 4 channels. A total of 16 channels. Following types are |
| supported: |
| 0 - TX channel with 32bit transmit register and IRQ transmit |
| acknowledgment support. |
| 1 - RX channel with 32bit receive register and IRQ support |
| 2 - TX doorbell channel. Without own register and no ACK support. |
| 3 - RX doorbell channel. |
| const: 2 |
| |
| clocks: |
| maxItems: 1 |
| |
| fsl,mu-side-b: |
| description: boolean, if present, means it is for side B MU. |
| type: boolean |
| |
| power-domains: |
| maxItems: 1 |
| |
| required: |
| - compatible |
| - reg |
| - interrupts |
| - "#mbox-cells" |
| |
| additionalProperties: false |
| |
| examples: |
| - | |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| |
| mailbox@5d1b0000 { |
| compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; |
| reg = <0x5d1b0000 0x10000>; |
| interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; |
| #mbox-cells = <2>; |
| }; |