| // SPDX-License-Identifier: GPL-2.0-only OR MIT |
| /** |
| * DT overlay for enabling 2nd ICSSG1 port on AM642 EVM |
| * |
| * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ |
| */ |
| |
| /dts-v1/; |
| /plugin/; |
| |
| #include <dt-bindings/gpio/gpio.h> |
| #include "k3-pinctrl.h" |
| |
| &{/} { |
| aliases { |
| ethernet1 = "/icssg1-eth/ethernet-ports/port@1"; |
| }; |
| |
| mdio-mux-2 { |
| compatible = "mdio-mux-multiplexer"; |
| mux-controls = <&mdio_mux>; |
| mdio-parent-bus = <&icssg1_mdio>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| mdio@0 { |
| reg = <0x0>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| icssg1_phy2: ethernet-phy@3 { |
| reg = <3>; |
| tx-internal-delay-ps = <250>; |
| rx-internal-delay-ps = <2000>; |
| }; |
| }; |
| }; |
| }; |
| |
| &main_pmx0 { |
| icssg1_rgmii2_pins_default: icssg1-rgmii2-default-pins { |
| pinctrl-single,pins = < |
| AM64X_IOPAD(0x0108, PIN_INPUT, 2) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */ |
| AM64X_IOPAD(0x010c, PIN_INPUT, 2) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */ |
| AM64X_IOPAD(0x0110, PIN_INPUT, 2) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */ |
| AM64X_IOPAD(0x0114, PIN_INPUT, 2) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */ |
| AM64X_IOPAD(0x0120, PIN_INPUT, 2) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */ |
| AM64X_IOPAD(0x0118, PIN_INPUT, 2) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */ |
| AM64X_IOPAD(0x0134, PIN_OUTPUT, 2) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */ |
| AM64X_IOPAD(0x0138, PIN_OUTPUT, 2) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */ |
| AM64X_IOPAD(0x013c, PIN_OUTPUT, 2) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */ |
| AM64X_IOPAD(0x0140, PIN_OUTPUT, 2) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */ |
| AM64X_IOPAD(0x0148, PIN_OUTPUT, 2) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */ |
| AM64X_IOPAD(0x0144, PIN_OUTPUT, 2) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */ |
| >; |
| }; |
| }; |
| |
| &cpsw3g { |
| pinctrl-0 = <&rgmii1_pins_default>; |
| }; |
| |
| &cpsw_port2 { |
| status = "disabled"; |
| }; |
| |
| &mdio_mux_1 { |
| status = "disabled"; |
| }; |
| |
| &icssg1_eth { |
| pinctrl-0 = <&icssg1_rgmii1_pins_default>, <&icssg1_rgmii2_pins_default>; |
| }; |
| |
| &icssg1_emac1 { |
| status = "okay"; |
| phy-handle = <&icssg1_phy2>; |
| phy-mode = "rgmii-id"; |
| }; |