Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/firmware/xilinx/xlnx,zynqmp-firmware.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Xilinx firmware driver

maintainers:
  - Nava kishore Manne <nava.kishore.manne@amd.com>

description: The zynqmp-firmware node describes the interface to platform
  firmware. ZynqMP has an interface to communicate with secure firmware.
  Firmware driver provides an interface to firmware APIs. Interface APIs
  can be used by any driver to communicate to PMUFW(Platform Management Unit).
  These requests include clock management, pin control, device control,
  power management service, FPGA service and other platform management
  services.

properties:
  compatible:
    oneOf:
      - description: For implementations complying for Zynq Ultrascale+ MPSoC.
        const: xlnx,zynqmp-firmware

      - description: For implementations complying for Versal.
        const: xlnx,versal-firmware

      - description: For implementations complying for Versal NET.
        items:
          - enum:
              - xlnx,versal-net-firmware
          - const: xlnx,versal-firmware

  method:
    description: |
                 The method of calling the PM-API firmware layer.
                 Permitted values are.
                 - "smc" : SMC #0, following the SMCCC
                 - "hvc" : HVC #0, following the SMCCC

    $ref: /schemas/types.yaml#/definitions/string-array
    enum:
      - smc
      - hvc

  "#power-domain-cells":
    const: 1

  clock-controller:
    $ref: /schemas/clock/xlnx,versal-clk.yaml#
    description: The clock controller is a hardware block of Xilinx versal
      clock tree. It reads required input clock frequencies from the devicetree
      and acts as clock provider for all clock consumers of PS clocks.list of
      clock specifiers which are external input clocks to the given clock
      controller.
    type: object

  gpio:
    $ref: /schemas/gpio/xlnx,zynqmp-gpio-modepin.yaml#
    description: The gpio node describes connect to PS_MODE pins via firmware
      interface.
    type: object

  soc-nvmem:
    $ref: /schemas/nvmem/xlnx,zynqmp-nvmem.yaml#
    description: The ZynqMP MPSoC provides access to the hardware related data
      like SOC revision, IDCODE and specific purpose efuses.
    type: object

  pcap:
    $ref: /schemas/fpga/xlnx,zynqmp-pcap-fpga.yaml
    description: The ZynqMP SoC uses the PCAP (Processor Configuration Port) to
      configure the Programmable Logic (PL). The configuration uses the
      firmware interface.
    type: object

  pinctrl:
    $ref: /schemas/pinctrl/xlnx,zynqmp-pinctrl.yaml#
    description: The pinctrl node provides access to pinconfig and pincontrol
      functionality available in firmware.
    type: object

  power-management:
    $ref: /schemas/power/reset/xlnx,zynqmp-power.yaml#
    description: The zynqmp-power node describes the power management
      configurations. It will control remote suspend/shutdown interfaces.
    type: object

  reset-controller:
    $ref: /schemas/reset/xlnx,zynqmp-reset.yaml#
    description: The reset-controller node describes connection to the reset
      functionality via firmware interface.
    type: object

  versal-fpga:
    $ref: /schemas/fpga/xlnx,versal-fpga.yaml#
    description: Compatible of the FPGA device.
    type: object

  zynqmp-aes:
    $ref: /schemas/crypto/xlnx,zynqmp-aes.yaml#
    description: The ZynqMP AES-GCM hardened cryptographic accelerator is
      used to encrypt or decrypt the data with provided key and initialization
      vector.
    type: object

required:
  - compatible

additionalProperties: false

examples:
  - |
    #include <dt-bindings/power/xlnx-zynqmp-power.h>
    firmware {
      zynqmp_firmware: zynqmp-firmware {
        #power-domain-cells = <1>;
        soc-nvmem {
          compatible = "xlnx,zynqmp-nvmem-fw";
          nvmem-layout {
            compatible = "fixed-layout";
            #address-cells = <1>;
            #size-cells = <1>;

            soc_revision: soc-revision@0 {
                reg = <0x0 0x4>;
            };
          };
        };
        gpio {
          compatible = "xlnx,zynqmp-gpio-modepin";
          gpio-controller;
          #gpio-cells = <2>;
        };
        pcap {
          compatible = "xlnx,zynqmp-pcap-fpga";
        };
        pinctrl {
          compatible = "xlnx,zynqmp-pinctrl";
        };
        power-management {
          compatible = "xlnx,zynqmp-power";
          interrupts = <0 35 4>;
        };
        reset-controller {
          compatible = "xlnx,zynqmp-reset";
          #reset-cells = <1>;
        };
      };
    };

    sata {
      power-domains = <&zynqmp_firmware PD_SATA>;
    };

    versal-firmware {
      compatible = "xlnx,versal-firmware";
      method = "smc";

      versal_fpga: versal-fpga {
        compatible = "xlnx,versal-fpga";
      };

      xlnx_aes: zynqmp-aes {
        compatible = "xlnx,zynqmp-aes";
      };

      versal_clk: clock-controller {
        #clock-cells = <1>;
        compatible = "xlnx,versal-clk";
        clocks = <&ref>, <&pl_alt_ref>;
        clock-names = "ref", "pl_alt_ref";
      };
    };

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