Documentation/devicetree/bindings/gpio/sprd,gpio.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright 2022 Unisoc Inc.
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/sprd,gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Unisoc GPIO controller

maintainers:
  - Orson Zhai <orsonzhai@gmail.com>
  - Baolin Wang <baolin.wang7@gmail.com>
  - Chunyan Zhang <zhang.lyra@gmail.com>

description: |
  The controller's registers are organized as sets of sixteen 16-bit
  registers with each set controlling a bank of up to 16 pins. A single
  interrupt is shared for all of the banks handled by the controller.

properties:
  compatible:
    oneOf:
      - const: sprd,sc9860-gpio
      - items:
          - enum:
              - sprd,ums512-gpio
          - const: sprd,sc9860-gpio

  reg:
    maxItems: 1

  gpio-controller: true

  "#gpio-cells":
    const: 2

  interrupt-controller: true

  "#interrupt-cells":
    const: 2

  interrupts:
    maxItems: 1
    description: The interrupt shared by all GPIO lines for this controller.

required:
  - compatible
  - reg
  - gpio-controller
  - "#gpio-cells"
  - interrupt-controller
  - "#interrupt-cells"
  - interrupts

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        ap_gpio: gpio@40280000 {
            compatible = "sprd,sc9860-gpio";
            reg = <0 0x40280000 0 0x1000>;
            gpio-controller;
            #gpio-cells = <2>;
            interrupt-controller;
            #interrupt-cells = <2>;
            interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
        };
    };
...