| /* |
| * Allwinner a83t SoCs pinctrl driver. |
| * |
| * Copyright (C) 2015 Vishnu Patekar <vishnupatekar0510@gmail.com> |
| * |
| * Based on pinctrl-sun8i-a23.c, which is: |
| * Copyright (C) 2014 Chen-Yu Tsai <wens@csie.org> |
| * Copyright (C) 2014 Maxime Ripard <maxime.ripard@free-electrons.com> |
| * |
| * This file is licensed under the terms of the GNU General Public |
| * License version 2. This program is licensed "as is" without any |
| * warranty of any kind, whether express or implied. |
| */ |
| |
| #include <linux/init.h> |
| #include <linux/platform_device.h> |
| #include <linux/of.h> |
| #include <linux/pinctrl/pinctrl.h> |
| |
| #include "pinctrl-sunxi.h" |
| |
| static const struct sunxi_desc_pin sun8i_a83t_pins[] = { |
| /* Hole */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "uart2"), /* TX */ |
| SUNXI_FUNCTION(0x3, "jtag"), /* MS0 */ |
| SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PB_EINT0 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "uart2"), /* RX */ |
| SUNXI_FUNCTION(0x3, "jtag"), /* CK0 */ |
| SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PB_EINT1 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "uart2"), /* RTS */ |
| SUNXI_FUNCTION(0x3, "jtag"), /* DO0 */ |
| SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PB_EINT2 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "uart2"), /* CTS */ |
| SUNXI_FUNCTION(0x3, "jtag"), /* DI0 */ |
| SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PB_EINT3 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "i2s0"), /* LRCK */ |
| SUNXI_FUNCTION(0x3, "tdm"), /* LRCK */ |
| SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PB_EINT4 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "i2s0"), /* BCLK */ |
| SUNXI_FUNCTION(0x3, "tdm"), /* BCLK */ |
| SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PB_EINT5 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "i2s0"), /* DOUT */ |
| SUNXI_FUNCTION(0x3, "tdm"), /* DOUT */ |
| SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PB_EINT6 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "i2s0"), /* DIN */ |
| SUNXI_FUNCTION(0x3, "tdm"), /* DIN */ |
| SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PB_EINT7 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "i2s0"), /* MCLK */ |
| SUNXI_FUNCTION(0x3, "tdm"), /* MCLK */ |
| SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PB_EINT8 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "uart0"), /* TX */ |
| SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PB_EINT9 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "uart0"), /* RX */ |
| SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PB_EINT10 */ |
| /* Hole */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "nand0"), /* WE */ |
| SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "nand0"), /* ALE */ |
| SUNXI_FUNCTION(0x3, "spi0")), /* MISO */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "nand0"), /* CLE */ |
| SUNXI_FUNCTION(0x3, "spi0")), /* CLK */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "nand0"), /* CE1 */ |
| SUNXI_FUNCTION(0x3, "spi0")), /* CS */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "nand0")), /* CE0 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "nand0"), /* RE */ |
| SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */ |
| SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "nand0")), /* RB1 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */ |
| SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */ |
| SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */ |
| SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */ |
| SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */ |
| SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */ |
| SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */ |
| SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */ |
| SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "nand0"), /* DQS */ |
| SUNXI_FUNCTION(0x3, "mmc2")), /* RST */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 17), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "nand0")), /* CE2 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 18), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "nand0")), /* CE3 */ |
| /* Hole */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */ |
| SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII RXD3 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */ |
| SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII RXD2 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */ |
| SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII RXD1 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */ |
| SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII RXD0 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */ |
| SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII RXCK */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */ |
| SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII RXDV */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */ |
| SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII RXERR */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */ |
| SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII TXD3 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */ |
| SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII TXD2 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */ |
| SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII TXD1 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */ |
| SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII TXD0 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */ |
| SUNXI_FUNCTION(0x4, "gmac")), /* RGMII-NULL / MII-CRS */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */ |
| SUNXI_FUNCTION(0x3, "lvds0"), /* VP0 */ |
| SUNXI_FUNCTION(0x4, "gmac")), /* GTXCK / ETXCK */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */ |
| SUNXI_FUNCTION(0x3, "lvds0"), /* VN0 */ |
| SUNXI_FUNCTION(0x4, "gmac")), /* GTXCTL / ETXEL */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */ |
| SUNXI_FUNCTION(0x3, "lvds0"), /* VP1 */ |
| SUNXI_FUNCTION(0x4, "gmac")), /* GNULL / ETXERR */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */ |
| SUNXI_FUNCTION(0x3, "lvds0"), /* VN1 */ |
| SUNXI_FUNCTION(0x4, "gmac")), /* GCLKIN / ECOL */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */ |
| SUNXI_FUNCTION(0x3, "lvds0"), /* VP2 */ |
| SUNXI_FUNCTION(0x4, "gmac")), /* GMDC */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */ |
| SUNXI_FUNCTION(0x3, "lvds0"), /* VN2 */ |
| SUNXI_FUNCTION(0x4, "gmac")), /* GMDIO */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */ |
| SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "lcd0"), /* DE */ |
| SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */ |
| SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */ |
| SUNXI_FUNCTION(0x3, "lvds0")), /* VN3 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 28), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "pwm")), /* PWM */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 29), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out")), |
| /* Hole */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "csi"), /* PCLK */ |
| SUNXI_FUNCTION(0x4, "ccir")), /* CLK */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "csi"), /* MCLK */ |
| SUNXI_FUNCTION(0x4, "ccir")), /* DE */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */ |
| SUNXI_FUNCTION(0x4, "ccir")), /* HSYNC */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */ |
| SUNXI_FUNCTION(0x4, "ccir")), /* VSYNC */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "csi")), /* D0 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "csi")), /* D1 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "csi"), /* D2 */ |
| SUNXI_FUNCTION(0x4, "ccir")), /* D0 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "csi"), /* D3 */ |
| SUNXI_FUNCTION(0x4, "ccir")), /* D1 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "csi"), /* D4 */ |
| SUNXI_FUNCTION(0x4, "ccir")), /* D2 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "csi"), /* D5 */ |
| SUNXI_FUNCTION(0x4, "ccir")), /* D3 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "csi"), /* D6 */ |
| SUNXI_FUNCTION(0x3, "uart4"), /* TX */ |
| SUNXI_FUNCTION(0x4, "ccir")), /* D4 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "csi"), /* D7 */ |
| SUNXI_FUNCTION(0x3, "uart4"), /* RX */ |
| SUNXI_FUNCTION(0x4, "ccir")), /* D5 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "csi"), /* D8 */ |
| SUNXI_FUNCTION(0x3, "uart4"), /* RTS */ |
| SUNXI_FUNCTION(0x4, "ccir")), /* D6 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "csi"), /* D9 */ |
| SUNXI_FUNCTION(0x3, "uart4"), /* CTS */ |
| SUNXI_FUNCTION(0x4, "ccir")), /* D7 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "csi"), /* SCK */ |
| SUNXI_FUNCTION(0x3, "i2c2")), /* SCK */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "csi"), /* SDA */ |
| SUNXI_FUNCTION(0x3, "i2c2")), /* SDA */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out")), |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 17), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out")), |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 18), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x3, "spdif")), /* DOUT */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 19), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out")), |
| /* Hole */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */ |
| SUNXI_FUNCTION(0x3, "jtag")), /* MS1 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */ |
| SUNXI_FUNCTION(0x3, "jtag")), /* DI1 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */ |
| SUNXI_FUNCTION(0x3, "uart0")), /* TX */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */ |
| SUNXI_FUNCTION(0x3, "jtag")), /* DO1 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */ |
| SUNXI_FUNCTION(0x3, "uart0")), /* RX */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */ |
| SUNXI_FUNCTION(0x3, "jtag")), /* CK1 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out")), |
| /* Hole */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */ |
| SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PG_EINT0 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */ |
| SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PG_EINT1 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */ |
| SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* PG_EINT2 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */ |
| SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PG_EINT3 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */ |
| SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PG_EINT4 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */ |
| SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PG_EINT5 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "uart1"), /* TX */ |
| SUNXI_FUNCTION(0x3, "spi1"), /* CS */ |
| SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PG_EINT6 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "uart1"), /* RX */ |
| SUNXI_FUNCTION(0x3, "spi1"), /* CLK */ |
| SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)), /* PG_EINT7 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "uart1"), /* RTS */ |
| SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */ |
| SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)), /* PG_EINT8 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "uart1"), /* CTS */ |
| SUNXI_FUNCTION(0x3, "spi1"), /* MISO */ |
| SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)), /* PG_EINT9 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "i2s1"), /* BCLK */ |
| SUNXI_FUNCTION(0x3, "uart3"), /* TX */ |
| SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)), /* PG_EINT10 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "i2s1"), /* LRCK */ |
| SUNXI_FUNCTION(0x3, "uart3"), /* RX */ |
| SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)), /* PG_EINT11 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "i2s1"), /* DOUT */ |
| SUNXI_FUNCTION(0x3, "uart3"), /* RTS */ |
| SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)), /* PG_EINT12 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "i2s1"), /* DIN */ |
| SUNXI_FUNCTION(0x3, "uart3"), /* CTS */ |
| SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 13)), /* PG_EINT13 */ |
| /* Hole */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */ |
| SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), /* PH_EINT0 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "i2c0"), /* SDA */ |
| SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), /* PH_EINT1 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "i2c1"), /* SCK */ |
| SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), /* PH_EINT2 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "i2c1"), /* SDA */ |
| SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), /* PH_EINT3 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "i2c2"), /* SCK */ |
| SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), /* PH_EINT4 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "i2c2"), /* SDA */ |
| SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), /* PH_EINT5 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "hdmi"), /* HSCL */ |
| SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)), /* PH_EINT6 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "hdmi"), /* HSDA */ |
| SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)), /* PH_EINT7 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION(0x2, "hdmi"), /* HCEC */ |
| SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)), /* PH_EINT8 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)), /* PH_EINT9 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), /* PH_EINT10 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), /* PH_EINT11 */ |
| }; |
| |
| static const struct sunxi_pinctrl_desc sun8i_a83t_pinctrl_data = { |
| .pins = sun8i_a83t_pins, |
| .npins = ARRAY_SIZE(sun8i_a83t_pins), |
| .irq_banks = 3, |
| }; |
| |
| static int sun8i_a83t_pinctrl_probe(struct platform_device *pdev) |
| { |
| return sunxi_pinctrl_init(pdev, |
| &sun8i_a83t_pinctrl_data); |
| } |
| |
| static const struct of_device_id sun8i_a83t_pinctrl_match[] = { |
| { .compatible = "allwinner,sun8i-a83t-pinctrl", }, |
| {} |
| }; |
| |
| static struct platform_driver sun8i_a83t_pinctrl_driver = { |
| .probe = sun8i_a83t_pinctrl_probe, |
| .driver = { |
| .name = "sun8i-a83t-pinctrl", |
| .of_match_table = sun8i_a83t_pinctrl_match, |
| }, |
| }; |
| builtin_platform_driver(sun8i_a83t_pinctrl_driver); |
