| /* |
| * Copyright 2011 Freescale Semiconductor, Inc. |
| * Copyright 2011 Linaro Ltd. |
| * |
| * The code contained herein is licensed under the GNU General Public |
| * License. You may obtain a copy of the GNU General Public License |
| * Version 2 or later at the following locations: |
| * |
| * http://www.opensource.org/licenses/gpl-license.html |
| * http://www.gnu.org/copyleft/gpl.html |
| */ |
| |
| /include/ "skeleton.dtsi" |
| |
| / { |
| aliases { |
| serial0 = &uart1; |
| serial1 = &uart2; |
| serial2 = &uart3; |
| serial3 = &uart4; |
| serial4 = &uart5; |
| gpio0 = &gpio1; |
| gpio1 = &gpio2; |
| gpio2 = &gpio3; |
| gpio3 = &gpio4; |
| gpio4 = &gpio5; |
| gpio5 = &gpio6; |
| gpio6 = &gpio7; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu@0 { |
| compatible = "arm,cortex-a9"; |
| reg = <0>; |
| next-level-cache = <&L2>; |
| operating-points = < |
| /* kHz uV */ |
| 792000 1100000 |
| 396000 950000 |
| 198000 850000 |
| >; |
| clock-latency = <61036>; /* two CLK32 periods */ |
| cpu0-supply = <®_cpu>; |
| }; |
| |
| cpu@1 { |
| compatible = "arm,cortex-a9"; |
| reg = <1>; |
| next-level-cache = <&L2>; |
| }; |
| |
| cpu@2 { |
| compatible = "arm,cortex-a9"; |
| reg = <2>; |
| next-level-cache = <&L2>; |
| }; |
| |
| cpu@3 { |
| compatible = "arm,cortex-a9"; |
| reg = <3>; |
| next-level-cache = <&L2>; |
| }; |
| }; |
| |
| intc: interrupt-controller@00a01000 { |
| compatible = "arm,cortex-a9-gic"; |
| #interrupt-cells = <3>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| interrupt-controller; |
| reg = <0x00a01000 0x1000>, |
| <0x00a00100 0x100>; |
| }; |
| |
| clocks { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| ckil { |
| compatible = "fsl,imx-ckil", "fixed-clock"; |
| clock-frequency = <32768>; |
| }; |
| |
| ckih1 { |
| compatible = "fsl,imx-ckih1", "fixed-clock"; |
| clock-frequency = <0>; |
| }; |
| |
| osc { |
| compatible = "fsl,imx-osc", "fixed-clock"; |
| clock-frequency = <24000000>; |
| }; |
| }; |
| |
| soc { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "simple-bus"; |
| interrupt-parent = <&intc>; |
| ranges; |
| |
| dma-apbh@00110000 { |
| compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; |
| reg = <0x00110000 0x2000>; |
| clocks = <&clks 106>; |
| }; |
| |
| nfc: gpmi-nand@00112000 { |
| compatible = "fsl,imx6q-gpmi-nand"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| reg = <0x00112000 0x2000>, <0x00114000 0x2000>; |
| reg-names = "gpmi-nand", "bch"; |
| interrupts = <0 13 0x04>, <0 15 0x04>; |
| interrupt-names = "gpmi-dma", "bch"; |
| clocks = <&clks 152>, <&clks 153>, <&clks 151>, |
| <&clks 150>, <&clks 149>; |
| clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", |
| "gpmi_bch_apb", "per1_bch"; |
| fsl,gpmi-dma-channel = <0>; |
| status = "disabled"; |
| }; |
| |
| timer@00a00600 { |
| compatible = "arm,cortex-a9-twd-timer"; |
| reg = <0x00a00600 0x20>; |
| interrupts = <1 13 0xf01>; |
| }; |
| |
| L2: l2-cache@00a02000 { |
| compatible = "arm,pl310-cache"; |
| reg = <0x00a02000 0x1000>; |
| interrupts = <0 92 0x04>; |
| cache-unified; |
| cache-level = <2>; |
| }; |
| |
| aips-bus@02000000 { /* AIPS1 */ |
| compatible = "fsl,aips-bus", "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| reg = <0x02000000 0x100000>; |
| ranges; |
| |
| spba-bus@02000000 { |
| compatible = "fsl,spba-bus", "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| reg = <0x02000000 0x40000>; |
| ranges; |
| |
| spdif: spdif@02004000 { |
| reg = <0x02004000 0x4000>; |
| interrupts = <0 52 0x04>; |
| }; |
| |
| ecspi1: ecspi@02008000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; |
| reg = <0x02008000 0x4000>; |
| interrupts = <0 31 0x04>; |
| clocks = <&clks 112>, <&clks 112>; |
| clock-names = "ipg", "per"; |
| status = "disabled"; |
| }; |
| |
| ecspi2: ecspi@0200c000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; |
| reg = <0x0200c000 0x4000>; |
| interrupts = <0 32 0x04>; |
| clocks = <&clks 113>, <&clks 113>; |
| clock-names = "ipg", "per"; |
| status = "disabled"; |
| }; |
| |
| ecspi3: ecspi@02010000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; |
| reg = <0x02010000 0x4000>; |
| interrupts = <0 33 0x04>; |
| clocks = <&clks 114>, <&clks 114>; |
| clock-names = "ipg", "per"; |
| status = "disabled"; |
| }; |
| |
| ecspi4: ecspi@02014000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; |
| reg = <0x02014000 0x4000>; |
| interrupts = <0 34 0x04>; |
| clocks = <&clks 115>, <&clks 115>; |
| clock-names = "ipg", "per"; |
| status = "disabled"; |
| }; |
| |
| ecspi5: ecspi@02018000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; |
| reg = <0x02018000 0x4000>; |
| interrupts = <0 35 0x04>; |
| clocks = <&clks 116>, <&clks 116>; |
| clock-names = "ipg", "per"; |
| status = "disabled"; |
| }; |
| |
| uart1: serial@02020000 { |
| compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
| reg = <0x02020000 0x4000>; |
| interrupts = <0 26 0x04>; |
| clocks = <&clks 160>, <&clks 161>; |
| clock-names = "ipg", "per"; |
| status = "disabled"; |
| }; |
| |
| esai: esai@02024000 { |
| reg = <0x02024000 0x4000>; |
| interrupts = <0 51 0x04>; |
| }; |
| |
| ssi1: ssi@02028000 { |
| compatible = "fsl,imx6q-ssi","fsl,imx21-ssi"; |
| reg = <0x02028000 0x4000>; |
| interrupts = <0 46 0x04>; |
| clocks = <&clks 178>; |
| fsl,fifo-depth = <15>; |
| fsl,ssi-dma-events = <38 37>; |
| status = "disabled"; |
| }; |
| |
| ssi2: ssi@0202c000 { |
| compatible = "fsl,imx6q-ssi","fsl,imx21-ssi"; |
| reg = <0x0202c000 0x4000>; |
| interrupts = <0 47 0x04>; |
| clocks = <&clks 179>; |
| fsl,fifo-depth = <15>; |
| fsl,ssi-dma-events = <42 41>; |
| status = "disabled"; |
| }; |
| |
| ssi3: ssi@02030000 { |
| compatible = "fsl,imx6q-ssi","fsl,imx21-ssi"; |
| reg = <0x02030000 0x4000>; |
| interrupts = <0 48 0x04>; |
| clocks = <&clks 180>; |
| fsl,fifo-depth = <15>; |
| fsl,ssi-dma-events = <46 45>; |
| status = "disabled"; |
| }; |
| |
| asrc: asrc@02034000 { |
| reg = <0x02034000 0x4000>; |
| interrupts = <0 50 0x04>; |
| }; |
| |
| spba@0203c000 { |
| reg = <0x0203c000 0x4000>; |
| }; |
| }; |
| |
| vpu: vpu@02040000 { |
| reg = <0x02040000 0x3c000>; |
| interrupts = <0 3 0x04 0 12 0x04>; |
| }; |
| |
| aipstz@0207c000 { /* AIPSTZ1 */ |
| reg = <0x0207c000 0x4000>; |
| }; |
| |
| pwm1: pwm@02080000 { |
| #pwm-cells = <2>; |
| compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; |
| reg = <0x02080000 0x4000>; |
| interrupts = <0 83 0x04>; |
| clocks = <&clks 62>, <&clks 145>; |
| clock-names = "ipg", "per"; |
| }; |
| |
| pwm2: pwm@02084000 { |
| #pwm-cells = <2>; |
| compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; |
| reg = <0x02084000 0x4000>; |
| interrupts = <0 84 0x04>; |
| clocks = <&clks 62>, <&clks 146>; |
| clock-names = "ipg", "per"; |
| }; |
| |
| pwm3: pwm@02088000 { |
| #pwm-cells = <2>; |
| compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; |
| reg = <0x02088000 0x4000>; |
| interrupts = <0 85 0x04>; |
| clocks = <&clks 62>, <&clks 147>; |
| clock-names = "ipg", "per"; |
| }; |
| |
| pwm4: pwm@0208c000 { |
| #pwm-cells = <2>; |
| compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; |
| reg = <0x0208c000 0x4000>; |
| interrupts = <0 86 0x04>; |
| clocks = <&clks 62>, <&clks 148>; |
| clock-names = "ipg", "per"; |
| }; |
| |
| can1: flexcan@02090000 { |
| reg = <0x02090000 0x4000>; |
| interrupts = <0 110 0x04>; |
| }; |
| |
| can2: flexcan@02094000 { |
| reg = <0x02094000 0x4000>; |
| interrupts = <0 111 0x04>; |
| }; |
| |
| gpt: gpt@02098000 { |
| compatible = "fsl,imx6q-gpt"; |
| reg = <0x02098000 0x4000>; |
| interrupts = <0 55 0x04>; |
| }; |
| |
| gpio1: gpio@0209c000 { |
| compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
| reg = <0x0209c000 0x4000>; |
| interrupts = <0 66 0x04 0 67 0x04>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| |
| gpio2: gpio@020a0000 { |
| compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
| reg = <0x020a0000 0x4000>; |
| interrupts = <0 68 0x04 0 69 0x04>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| |
| gpio3: gpio@020a4000 { |
| compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
| reg = <0x020a4000 0x4000>; |
| interrupts = <0 70 0x04 0 71 0x04>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| |
| gpio4: gpio@020a8000 { |
| compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
| reg = <0x020a8000 0x4000>; |
| interrupts = <0 72 0x04 0 73 0x04>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| |
| gpio5: gpio@020ac000 { |
| compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
| reg = <0x020ac000 0x4000>; |
| interrupts = <0 74 0x04 0 75 0x04>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| |
| gpio6: gpio@020b0000 { |
| compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
| reg = <0x020b0000 0x4000>; |
| interrupts = <0 76 0x04 0 77 0x04>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| |
| gpio7: gpio@020b4000 { |
| compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
| reg = <0x020b4000 0x4000>; |
| interrupts = <0 78 0x04 0 79 0x04>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| |
| kpp: kpp@020b8000 { |
| reg = <0x020b8000 0x4000>; |
| interrupts = <0 82 0x04>; |
| }; |
| |
| wdog1: wdog@020bc000 { |
| compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; |
| reg = <0x020bc000 0x4000>; |
| interrupts = <0 80 0x04>; |
| clocks = <&clks 0>; |
| }; |
| |
| wdog2: wdog@020c0000 { |
| compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; |
| reg = <0x020c0000 0x4000>; |
| interrupts = <0 81 0x04>; |
| clocks = <&clks 0>; |
| status = "disabled"; |
| }; |
| |
| clks: ccm@020c4000 { |
| compatible = "fsl,imx6q-ccm"; |
| reg = <0x020c4000 0x4000>; |
| interrupts = <0 87 0x04 0 88 0x04>; |
| #clock-cells = <1>; |
| }; |
| |
| anatop: anatop@020c8000 { |
| compatible = "fsl,imx6q-anatop", "syscon", "simple-bus"; |
| reg = <0x020c8000 0x1000>; |
| interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>; |
| |
| regulator-1p1@110 { |
| compatible = "fsl,anatop-regulator"; |
| regulator-name = "vdd1p1"; |
| regulator-min-microvolt = <800000>; |
| regulator-max-microvolt = <1375000>; |
| regulator-always-on; |
| anatop-reg-offset = <0x110>; |
| anatop-vol-bit-shift = <8>; |
| anatop-vol-bit-width = <5>; |
| anatop-min-bit-val = <4>; |
| anatop-min-voltage = <800000>; |
| anatop-max-voltage = <1375000>; |
| }; |
| |
| regulator-3p0@120 { |
| compatible = "fsl,anatop-regulator"; |
| regulator-name = "vdd3p0"; |
| regulator-min-microvolt = <2800000>; |
| regulator-max-microvolt = <3150000>; |
| regulator-always-on; |
| anatop-reg-offset = <0x120>; |
| anatop-vol-bit-shift = <8>; |
| anatop-vol-bit-width = <5>; |
| anatop-min-bit-val = <0>; |
| anatop-min-voltage = <2625000>; |
| anatop-max-voltage = <3400000>; |
| }; |
| |
| regulator-2p5@130 { |
| compatible = "fsl,anatop-regulator"; |
| regulator-name = "vdd2p5"; |
| regulator-min-microvolt = <2000000>; |
| regulator-max-microvolt = <2750000>; |
| regulator-always-on; |
| anatop-reg-offset = <0x130>; |
| anatop-vol-bit-shift = <8>; |
| anatop-vol-bit-width = <5>; |
| anatop-min-bit-val = <0>; |
| anatop-min-voltage = <2000000>; |
| anatop-max-voltage = <2750000>; |
| }; |
| |
| reg_cpu: regulator-vddcore@140 { |
| compatible = "fsl,anatop-regulator"; |
| regulator-name = "cpu"; |
| regulator-min-microvolt = <725000>; |
| regulator-max-microvolt = <1450000>; |
| regulator-always-on; |
| anatop-reg-offset = <0x140>; |
| anatop-vol-bit-shift = <0>; |
| anatop-vol-bit-width = <5>; |
| anatop-min-bit-val = <1>; |
| anatop-min-voltage = <725000>; |
| anatop-max-voltage = <1450000>; |
| }; |
| |
| regulator-vddpu@140 { |
| compatible = "fsl,anatop-regulator"; |
| regulator-name = "vddpu"; |
| regulator-min-microvolt = <725000>; |
| regulator-max-microvolt = <1450000>; |
| regulator-always-on; |
| anatop-reg-offset = <0x140>; |
| anatop-vol-bit-shift = <9>; |
| anatop-vol-bit-width = <5>; |
| anatop-min-bit-val = <1>; |
| anatop-min-voltage = <725000>; |
| anatop-max-voltage = <1450000>; |
| }; |
| |
| regulator-vddsoc@140 { |
| compatible = "fsl,anatop-regulator"; |
| regulator-name = "vddsoc"; |
| regulator-min-microvolt = <725000>; |
| regulator-max-microvolt = <1450000>; |
| regulator-always-on; |
| anatop-reg-offset = <0x140>; |
| anatop-vol-bit-shift = <18>; |
| anatop-vol-bit-width = <5>; |
| anatop-min-bit-val = <1>; |
| anatop-min-voltage = <725000>; |
| anatop-max-voltage = <1450000>; |
| }; |
| }; |
| |
| usbphy1: usbphy@020c9000 { |
| compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; |
| reg = <0x020c9000 0x1000>; |
| interrupts = <0 44 0x04>; |
| clocks = <&clks 182>; |
| }; |
| |
| usbphy2: usbphy@020ca000 { |
| compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; |
| reg = <0x020ca000 0x1000>; |
| interrupts = <0 45 0x04>; |
| clocks = <&clks 183>; |
| }; |
| |
| snvs@020cc000 { |
| compatible = "fsl,sec-v4.0-mon", "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 0x020cc000 0x4000>; |
| |
| snvs-rtc-lp@34 { |
| compatible = "fsl,sec-v4.0-mon-rtc-lp"; |
| reg = <0x34 0x58>; |
| interrupts = <0 19 0x04 0 20 0x04>; |
| }; |
| }; |
| |
| epit1: epit@020d0000 { /* EPIT1 */ |
| reg = <0x020d0000 0x4000>; |
| interrupts = <0 56 0x04>; |
| }; |
| |
| epit2: epit@020d4000 { /* EPIT2 */ |
| reg = <0x020d4000 0x4000>; |
| interrupts = <0 57 0x04>; |
| }; |
| |
| src: src@020d8000 { |
| compatible = "fsl,imx6q-src"; |
| reg = <0x020d8000 0x4000>; |
| interrupts = <0 91 0x04 0 96 0x04>; |
| }; |
| |
| gpc: gpc@020dc000 { |
| compatible = "fsl,imx6q-gpc"; |
| reg = <0x020dc000 0x4000>; |
| interrupts = <0 89 0x04 0 90 0x04>; |
| }; |
| |
| gpr: iomuxc-gpr@020e0000 { |
| compatible = "fsl,imx6q-iomuxc-gpr", "syscon"; |
| reg = <0x020e0000 0x38>; |
| }; |
| |
| iomuxc: iomuxc@020e0000 { |
| compatible = "fsl,imx6q-iomuxc"; |
| reg = <0x020e0000 0x4000>; |
| |
| /* shared pinctrl settings */ |
| audmux { |
| pinctrl_audmux_1: audmux-1 { |
| fsl,pins = < |
| 18 0x80000000 /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */ |
| 1586 0x80000000 /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */ |
| 11 0x80000000 /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */ |
| 3 0x80000000 /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */ |
| >; |
| }; |
| }; |
| |
| ecspi1 { |
| pinctrl_ecspi1_1: ecspi1grp-1 { |
| fsl,pins = < |
| 101 0x100b1 /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */ |
| 109 0x100b1 /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */ |
| 94 0x100b1 /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */ |
| >; |
| }; |
| }; |
| |
| enet { |
| pinctrl_enet_1: enetgrp-1 { |
| fsl,pins = < |
| 695 0x1b0b0 /* MX6Q_PAD_ENET_MDIO__ENET_MDIO */ |
| 756 0x1b0b0 /* MX6Q_PAD_ENET_MDC__ENET_MDC */ |
| 24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */ |
| 30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */ |
| 34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */ |
| 39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */ |
| 44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */ |
| 56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */ |
| 702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */ |
| 74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */ |
| 52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */ |
| 61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */ |
| 66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */ |
| 70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */ |
| 48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */ |
| 1033 0x4001b0a8 /* MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT*/ |
| >; |
| }; |
| |
| pinctrl_enet_2: enetgrp-2 { |
| fsl,pins = < |
| 890 0x1b0b0 /* MX6Q_PAD_KEY_COL1__ENET_MDIO */ |
| 909 0x1b0b0 /* MX6Q_PAD_KEY_COL2__ENET_MDC */ |
| 24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */ |
| 30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */ |
| 34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */ |
| 39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */ |
| 44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */ |
| 56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */ |
| 702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */ |
| 74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */ |
| 52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */ |
| 61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */ |
| 66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */ |
| 70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */ |
| 48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */ |
| >; |
| }; |
| }; |
| |
| gpmi-nand { |
| pinctrl_gpmi_nand_1: gpmi-nand-1 { |
| fsl,pins = < |
| 1328 0xb0b1 /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */ |
| 1336 0xb0b1 /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */ |
| 1344 0xb0b1 /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */ |
| 1352 0xb000 /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */ |
| 1360 0xb0b1 /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */ |
| 1365 0xb0b1 /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */ |
| 1371 0xb0b1 /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */ |
| 1378 0xb0b1 /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */ |
| 1387 0xb0b1 /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */ |
| 1393 0xb0b1 /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */ |
| 1397 0xb0b1 /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */ |
| 1405 0xb0b1 /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */ |
| 1413 0xb0b1 /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */ |
| 1421 0xb0b1 /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */ |
| 1429 0xb0b1 /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */ |
| 1437 0xb0b1 /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */ |
| 1445 0xb0b1 /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */ |
| 1453 0xb0b1 /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */ |
| 1463 0x00b1 /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */ |
| >; |
| }; |
| }; |
| |
| i2c1 { |
| pinctrl_i2c1_1: i2c1grp-1 { |
| fsl,pins = < |
| 137 0x4001b8b1 /* MX6Q_PAD_EIM_D21__I2C1_SCL */ |
| 196 0x4001b8b1 /* MX6Q_PAD_EIM_D28__I2C1_SDA */ |
| >; |
| }; |
| }; |
| |
| uart1 { |
| pinctrl_uart1_1: uart1grp-1 { |
| fsl,pins = < |
| 1140 0x1b0b1 /* MX6Q_PAD_CSI0_DAT10__UART1_TXD */ |
| 1148 0x1b0b1 /* MX6Q_PAD_CSI0_DAT11__UART1_RXD */ |
| >; |
| }; |
| }; |
| |
| uart2 { |
| pinctrl_uart2_1: uart2grp-1 { |
| fsl,pins = < |
| 183 0x1b0b1 /* MX6Q_PAD_EIM_D26__UART2_TXD */ |
| 191 0x1b0b1 /* MX6Q_PAD_EIM_D27__UART2_RXD */ |
| >; |
| }; |
| }; |
| |
| uart4 { |
| pinctrl_uart4_1: uart4grp-1 { |
| fsl,pins = < |
| 877 0x1b0b1 /* MX6Q_PAD_KEY_COL0__UART4_TXD */ |
| 885 0x1b0b1 /* MX6Q_PAD_KEY_ROW0__UART4_RXD */ |
| >; |
| }; |
| }; |
| |
| usbotg { |
| pinctrl_usbotg_1: usbotggrp-1 { |
| fsl,pins = < |
| 1592 0x17059 /* MX6Q_PAD_GPIO_1__ANATOP_USBOTG_ID */ |
| >; |
| }; |
| }; |
| |
| usdhc2 { |
| pinctrl_usdhc2_1: usdhc2grp-1 { |
| fsl,pins = < |
| 1577 0x17059 /* MX6Q_PAD_SD2_CMD__USDHC2_CMD */ |
| 1569 0x10059 /* MX6Q_PAD_SD2_CLK__USDHC2_CLK */ |
| 16 0x17059 /* MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 */ |
| 0 0x17059 /* MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 */ |
| 8 0x17059 /* MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 */ |
| 1583 0x17059 /* MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 */ |
| 1430 0x17059 /* MX6Q_PAD_NANDF_D4__USDHC2_DAT4 */ |
| 1438 0x17059 /* MX6Q_PAD_NANDF_D5__USDHC2_DAT5 */ |
| 1446 0x17059 /* MX6Q_PAD_NANDF_D6__USDHC2_DAT6 */ |
| 1454 0x17059 /* MX6Q_PAD_NANDF_D7__USDHC2_DAT7 */ |
| >; |
| }; |
| }; |
| |
| usdhc3 { |
| pinctrl_usdhc3_1: usdhc3grp-1 { |
| fsl,pins = < |
| 1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */ |
| 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */ |
| 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */ |
| 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */ |
| 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */ |
| 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */ |
| 1265 0x17059 /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */ |
| 1257 0x17059 /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */ |
| 1249 0x17059 /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */ |
| 1241 0x17059 /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */ |
| >; |
| }; |
| |
| pinctrl_usdhc3_2: usdhc3grp-2 { |
| fsl,pins = < |
| 1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */ |
| 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */ |
| 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */ |
| 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */ |
| 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */ |
| 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */ |
| >; |
| }; |
| }; |
| |
| usdhc4 { |
| pinctrl_usdhc4_1: usdhc4grp-1 { |
| fsl,pins = < |
| 1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */ |
| 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */ |
| 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */ |
| 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */ |
| 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */ |
| 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */ |
| 1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */ |
| 1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */ |
| 1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */ |
| 1517 0x17059 /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */ |
| >; |
| }; |
| |
| pinctrl_usdhc4_2: usdhc4grp-2 { |
| fsl,pins = < |
| 1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */ |
| 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */ |
| 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */ |
| 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */ |
| 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */ |
| 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */ |
| >; |
| }; |
| }; |
| }; |
| |
| dcic1: dcic@020e4000 { |
| reg = <0x020e4000 0x4000>; |
| interrupts = <0 124 0x04>; |
| }; |
| |
| dcic2: dcic@020e8000 { |
| reg = <0x020e8000 0x4000>; |
| interrupts = <0 125 0x04>; |
| }; |
| |
| sdma: sdma@020ec000 { |
| compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma"; |
| reg = <0x020ec000 0x4000>; |
| interrupts = <0 2 0x04>; |
| clocks = <&clks 155>, <&clks 155>; |
| clock-names = "ipg", "ahb"; |
| fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q-to1.bin"; |
| }; |
| }; |
| |
| aips-bus@02100000 { /* AIPS2 */ |
| compatible = "fsl,aips-bus", "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| reg = <0x02100000 0x100000>; |
| ranges; |
| |
| caam@02100000 { |
| reg = <0x02100000 0x40000>; |
| interrupts = <0 105 0x04 0 106 0x04>; |
| }; |
| |
| aipstz@0217c000 { /* AIPSTZ2 */ |
| reg = <0x0217c000 0x4000>; |
| }; |
| |
| usbotg: usb@02184000 { |
| compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; |
| reg = <0x02184000 0x200>; |
| interrupts = <0 43 0x04>; |
| clocks = <&clks 162>; |
| fsl,usbphy = <&usbphy1>; |
| fsl,usbmisc = <&usbmisc 0>; |
| status = "disabled"; |
| }; |
| |
| usbh1: usb@02184200 { |
| compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; |
| reg = <0x02184200 0x200>; |
| interrupts = <0 40 0x04>; |
| clocks = <&clks 162>; |
| fsl,usbphy = <&usbphy2>; |
| fsl,usbmisc = <&usbmisc 1>; |
| status = "disabled"; |
| }; |
| |
| usbh2: usb@02184400 { |
| compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; |
| reg = <0x02184400 0x200>; |
| interrupts = <0 41 0x04>; |
| clocks = <&clks 162>; |
| fsl,usbmisc = <&usbmisc 2>; |
| status = "disabled"; |
| }; |
| |
| usbh3: usb@02184600 { |
| compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; |
| reg = <0x02184600 0x200>; |
| interrupts = <0 42 0x04>; |
| clocks = <&clks 162>; |
| fsl,usbmisc = <&usbmisc 3>; |
| status = "disabled"; |
| }; |
| |
| usbmisc: usbmisc: usbmisc@02184800 { |
| #index-cells = <1>; |
| compatible = "fsl,imx6q-usbmisc"; |
| reg = <0x02184800 0x200>; |
| clocks = <&clks 162>; |
| }; |
| |
| fec: ethernet@02188000 { |
| compatible = "fsl,imx6q-fec"; |
| reg = <0x02188000 0x4000>; |
| interrupts = <0 118 0x04 0 119 0x04>; |
| clocks = <&clks 117>, <&clks 117>, <&clks 177>; |
| clock-names = "ipg", "ahb", "ptp"; |
| status = "disabled"; |
| }; |
| |
| mlb@0218c000 { |
| reg = <0x0218c000 0x4000>; |
| interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>; |
| }; |
| |
| usdhc1: usdhc@02190000 { |
| compatible = "fsl,imx6q-usdhc"; |
| reg = <0x02190000 0x4000>; |
| interrupts = <0 22 0x04>; |
| clocks = <&clks 163>, <&clks 163>, <&clks 163>; |
| clock-names = "ipg", "ahb", "per"; |
| bus-width = <4>; |
| status = "disabled"; |
| }; |
| |
| usdhc2: usdhc@02194000 { |
| compatible = "fsl,imx6q-usdhc"; |
| reg = <0x02194000 0x4000>; |
| interrupts = <0 23 0x04>; |
| clocks = <&clks 164>, <&clks 164>, <&clks 164>; |
| clock-names = "ipg", "ahb", "per"; |
| bus-width = <4>; |
| status = "disabled"; |
| }; |
| |
| usdhc3: usdhc@02198000 { |
| compatible = "fsl,imx6q-usdhc"; |
| reg = <0x02198000 0x4000>; |
| interrupts = <0 24 0x04>; |
| clocks = <&clks 165>, <&clks 165>, <&clks 165>; |
| clock-names = "ipg", "ahb", "per"; |
| bus-width = <4>; |
| status = "disabled"; |
| }; |
| |
| usdhc4: usdhc@0219c000 { |
| compatible = "fsl,imx6q-usdhc"; |
| reg = <0x0219c000 0x4000>; |
| interrupts = <0 25 0x04>; |
| clocks = <&clks 166>, <&clks 166>, <&clks 166>; |
| clock-names = "ipg", "ahb", "per"; |
| bus-width = <4>; |
| status = "disabled"; |
| }; |
| |
| i2c1: i2c@021a0000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; |
| reg = <0x021a0000 0x4000>; |
| interrupts = <0 36 0x04>; |
| clocks = <&clks 125>; |
| status = "disabled"; |
| }; |
| |
| i2c2: i2c@021a4000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; |
| reg = <0x021a4000 0x4000>; |
| interrupts = <0 37 0x04>; |
| clocks = <&clks 126>; |
| status = "disabled"; |
| }; |
| |
| i2c3: i2c@021a8000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; |
| reg = <0x021a8000 0x4000>; |
| interrupts = <0 38 0x04>; |
| clocks = <&clks 127>; |
| status = "disabled"; |
| }; |
| |
| romcp@021ac000 { |
| reg = <0x021ac000 0x4000>; |
| }; |
| |
| mmdc0: mmdc@021b0000 { /* MMDC0 */ |
| compatible = "fsl,imx6q-mmdc"; |
| reg = <0x021b0000 0x4000>; |
| }; |
| |
| mmdc1: mmdc@021b4000 { /* MMDC1 */ |
| reg = <0x021b4000 0x4000>; |
| }; |
| |
| weim@021b8000 { |
| reg = <0x021b8000 0x4000>; |
| interrupts = <0 14 0x04>; |
| }; |
| |
| ocotp@021bc000 { |
| reg = <0x021bc000 0x4000>; |
| }; |
| |
| ocotp@021c0000 { |
| reg = <0x021c0000 0x4000>; |
| interrupts = <0 21 0x04>; |
| }; |
| |
| tzasc@021d0000 { /* TZASC1 */ |
| reg = <0x021d0000 0x4000>; |
| interrupts = <0 108 0x04>; |
| }; |
| |
| tzasc@021d4000 { /* TZASC2 */ |
| reg = <0x021d4000 0x4000>; |
| interrupts = <0 109 0x04>; |
| }; |
| |
| audmux: audmux@021d8000 { |
| compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux"; |
| reg = <0x021d8000 0x4000>; |
| status = "disabled"; |
| }; |
| |
| mipi@021dc000 { /* MIPI-CSI */ |
| reg = <0x021dc000 0x4000>; |
| }; |
| |
| mipi@021e0000 { /* MIPI-DSI */ |
| reg = <0x021e0000 0x4000>; |
| }; |
| |
| vdoa@021e4000 { |
| reg = <0x021e4000 0x4000>; |
| interrupts = <0 18 0x04>; |
| }; |
| |
| uart2: serial@021e8000 { |
| compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
| reg = <0x021e8000 0x4000>; |
| interrupts = <0 27 0x04>; |
| clocks = <&clks 160>, <&clks 161>; |
| clock-names = "ipg", "per"; |
| status = "disabled"; |
| }; |
| |
| uart3: serial@021ec000 { |
| compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
| reg = <0x021ec000 0x4000>; |
| interrupts = <0 28 0x04>; |
| clocks = <&clks 160>, <&clks 161>; |
| clock-names = "ipg", "per"; |
| status = "disabled"; |
| }; |
| |
| uart4: serial@021f0000 { |
| compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
| reg = <0x021f0000 0x4000>; |
| interrupts = <0 29 0x04>; |
| clocks = <&clks 160>, <&clks 161>; |
| clock-names = "ipg", "per"; |
| status = "disabled"; |
| }; |
| |
| uart5: serial@021f4000 { |
| compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
| reg = <0x021f4000 0x4000>; |
| interrupts = <0 30 0x04>; |
| clocks = <&clks 160>, <&clks 161>; |
| clock-names = "ipg", "per"; |
| status = "disabled"; |
| }; |
| }; |
| |
| ipu1: ipu@02400000 { |
| #crtc-cells = <1>; |
| compatible = "fsl,imx6q-ipu"; |
| reg = <0x02400000 0x400000>; |
| interrupts = <0 6 0x4 0 5 0x4>; |
| clocks = <&clks 130>, <&clks 131>, <&clks 132>; |
| clock-names = "bus", "di0", "di1"; |
| }; |
| |
| ipu2: ipu@02800000 { |
| #crtc-cells = <1>; |
| compatible = "fsl,imx6q-ipu"; |
| reg = <0x02800000 0x400000>; |
| interrupts = <0 8 0x4 0 7 0x4>; |
| clocks = <&clks 133>, <&clks 134>, <&clks 137>; |
| clock-names = "bus", "di0", "di1"; |
| }; |
| }; |
| }; |
