Documentation/devicetree/bindings/clock/imx8qxp-lpcg.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/imx8qxp-lpcg.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NXP i.MX8QXP LPCG (Low-Power Clock Gating) Clock bindings

maintainers:
  - Aisheng Dong <aisheng.dong@nxp.com>

description: |
  The Low-Power Clock Gate (LPCG) modules contain a local programming
  model to control the clock gates for the peripherals. An LPCG module
  is used to locally gate the clocks for the associated peripheral.

  This level of clock gating is provided after the clocks are generated
  by the SCU resources and clock controls. Thus even if the clock is
  enabled by these control bits, it might still not be running based
  on the base resource.

  The clock consumer should specify the desired clock by having the clock
  ID in its "clocks" phandle cell. See the full list of clock IDs from:
  include/dt-bindings/clock/imx8-clock.h

properties:
  compatible:
    enum:
      - fsl,imx8qxp-lpcg-adma
      - fsl,imx8qxp-lpcg-conn
      - fsl,imx8qxp-lpcg-dc
      - fsl,imx8qxp-lpcg-dsp
      - fsl,imx8qxp-lpcg-gpu
      - fsl,imx8qxp-lpcg-hsio
      - fsl,imx8qxp-lpcg-img
      - fsl,imx8qxp-lpcg-lsio
      - fsl,imx8qxp-lpcg-vpu

  reg:
    maxItems: 1

  '#clock-cells':
    const: 1

required:
  - compatible
  - reg
  - '#clock-cells'

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx8-clock.h>
    #include <dt-bindings/firmware/imx/rsrc.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    clock-controller@5b200000 {
        compatible = "fsl,imx8qxp-lpcg-conn";
        reg = <0x5b200000 0xb0000>;
        #clock-cells = <1>;
    };

    mmc@5b010000 {
        compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
        interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
        reg = <0x5b010000 0x10000>;
        clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK>,
                 <&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>,
                 <&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>;
        clock-names = "ipg", "per", "ahb";
        power-domains = <&pd IMX_SC_R_SDHC_0>;
    };