Documentation/devicetree/bindings/clock/rockchip,px30-cru.txt

* Rockchip PX30 Clock and Reset Unit

The PX30 clock controller generates and supplies clock to various
controllers within the SoC and also implements a reset controller for SoC
peripherals.

Required Properties:

- compatible: PMU for CRU should be "rockchip,px30-pmu-cru"
- compatible: CRU should be "rockchip,px30-cru"
- reg: physical base address of the controller and length of memory mapped
  region.
- clocks: A list of phandle + clock-specifier pairs for the clocks listed
          in clock-names
- clock-names: Should contain the following:
  - "xin24m" for both PMUCRU and CRU
  - "gpll" for CRU (sourced from PMUCRU)
- #clock-cells: should be 1.
- #reset-cells: should be 1.

Optional Properties:

- rockchip,grf: phandle to the syscon managing the "general register files"
  If missing, pll rates are not changeable, due to the missing pll lock status.

Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. All available clocks are defined as
preprocessor macros in the dt-bindings/clock/px30-cru.h headers and can be
used in device tree sources. Similar macros exist for the reset sources in
these files.

External clocks:

There are several clocks that are generated outside the SoC. It is expected
that they are defined using standard clock bindings with following
clock-output-names:
 - "xin24m" - crystal input - required,
 - "xin32k" - rtc clock - optional,
 - "i2sx_clkin" - external I2S clock - optional,
 - "gmac_clkin" - external GMAC clock - optional

Example: Clock controller node:

	pmucru: clock-controller@ff2bc000 {
		compatible = "rockchip,px30-pmucru";
		reg = <0x0 0xff2bc000 0x0 0x1000>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	cru: clock-controller@ff2b0000 {
		compatible = "rockchip,px30-cru";
		reg = <0x0 0xff2b0000 0x0 0x1000>;
		rockchip,grf = <&grf>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

Example: UART controller node that consumes the clock generated by the clock
  controller:

	uart0: serial@ff030000 {
		compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
		reg = <0x0 0xff030000 0x0 0x100>;
		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>;
		clock-names = "baudclk", "apb_pclk";
		reg-shift = <2>;
		reg-io-width = <4>;
	};