| # SPDX-License-Identifier: GPL-2.0 |
| %YAML 1.2 |
| --- |
| $id: http://devicetree.org/schemas/pci/snps,dw-pcie-ep.yaml# |
| $schema: http://devicetree.org/meta-schemas/core.yaml# |
| |
| title: Synopsys DesignWare PCIe endpoint interface |
| |
| maintainers: |
| - Jingoo Han <jingoohan1@gmail.com> |
| - Gustavo Pimentel <gustavo.pimentel@synopsys.com> |
| |
| description: | |
| Synopsys DesignWare PCIe host controller endpoint |
| |
| allOf: |
| - $ref: /schemas/pci/pci-ep.yaml# |
| |
| properties: |
| compatible: |
| anyOf: |
| - {} |
| - const: snps,dw-pcie-ep |
| |
| reg: |
| description: | |
| It should contain Data Bus Interface (dbi) and config registers for all |
| versions. |
| For designware core version >= 4.80, it may contain ATU address space. |
| minItems: 2 |
| maxItems: 4 |
| |
| reg-names: |
| minItems: 2 |
| maxItems: 4 |
| items: |
| enum: [dbi, dbi2, config, atu, addr_space, link, atu_dma, appl] |
| |
| reset-gpio: |
| description: GPIO pin number of PERST# signal |
| maxItems: 1 |
| deprecated: true |
| |
| reset-gpios: |
| description: GPIO controlled connection to PERST# signal |
| maxItems: 1 |
| |
| snps,enable-cdm-check: |
| type: boolean |
| description: | |
| This is a boolean property and if present enables |
| automatic checking of CDM (Configuration Dependent Module) registers |
| for data corruption. CDM registers include standard PCIe configuration |
| space registers, Port Logic registers, DMA and iATU (internal Address |
| Translation Unit) registers. |
| |
| num-ib-windows: |
| description: number of inbound address translation windows |
| maxItems: 1 |
| deprecated: true |
| |
| num-ob-windows: |
| description: number of outbound address translation windows |
| maxItems: 1 |
| deprecated: true |
| |
| max-functions: |
| $ref: /schemas/types.yaml#/definitions/uint32 |
| description: maximum number of functions that can be configured |
| |
| required: |
| - reg |
| - reg-names |
| - compatible |
| |
| unevaluatedProperties: false |
| |
| examples: |
| - | |
| bus { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| pcie-ep@dfd00000 { |
| compatible = "snps,dw-pcie-ep"; |
| reg = <0xdfc00000 0x0001000>, /* IP registers 1 */ |
| <0xdfc01000 0x0001000>, /* IP registers 2 */ |
| <0xd0000000 0x2000000>; /* Configuration space */ |
| reg-names = "dbi", "dbi2", "addr_space"; |
| }; |
| }; |