| // SPDX-License-Identifier: GPL-2.0-or-later OR MIT |
| /* |
| * Device Tree file for Globalscale MOCHAbin |
| * Copyright (C) 2019 Globalscale technologies, Inc. |
| * Copyright (C) 2021 Sartura Ltd. |
| * |
| */ |
| |
| /dts-v1/; |
| |
| #include <dt-bindings/gpio/gpio.h> |
| #include "armada-7040.dtsi" |
| |
| / { |
| model = "Globalscale MOCHAbin"; |
| compatible = "globalscale,mochabin", "marvell,armada7040", |
| "marvell,armada-ap806-quad", "marvell,armada-ap806"; |
| |
| chosen { |
| stdout-path = "serial0:115200n8"; |
| }; |
| |
| aliases { |
| ethernet0 = &cp0_eth0; |
| ethernet1 = &cp0_eth1; |
| ethernet2 = &cp0_eth2; |
| ethernet3 = &swport1; |
| ethernet4 = &swport2; |
| ethernet5 = &swport3; |
| ethernet6 = &swport4; |
| }; |
| |
| /* SFP+ 10G */ |
| sfp_eth0: sfp-eth0 { |
| compatible = "sff,sfp"; |
| i2c-bus = <&cp0_i2c1>; |
| los-gpio = <&sfp_gpio 3 GPIO_ACTIVE_HIGH>; |
| mod-def0-gpio = <&sfp_gpio 2 GPIO_ACTIVE_LOW>; |
| tx-disable-gpio = <&sfp_gpio 1 GPIO_ACTIVE_HIGH>; |
| tx-fault-gpio = <&sfp_gpio 0 GPIO_ACTIVE_HIGH>; |
| }; |
| |
| /* SFP 1G */ |
| sfp_eth2: sfp-eth2 { |
| compatible = "sff,sfp"; |
| i2c-bus = <&cp0_i2c0>; |
| los-gpio = <&sfp_gpio 7 GPIO_ACTIVE_HIGH>; |
| mod-def0-gpio = <&sfp_gpio 6 GPIO_ACTIVE_LOW>; |
| tx-disable-gpio = <&sfp_gpio 5 GPIO_ACTIVE_HIGH>; |
| tx-fault-gpio = <&sfp_gpio 4 GPIO_ACTIVE_HIGH>; |
| }; |
| }; |
| |
| /* microUSB UART console */ |
| &uart0 { |
| status = "okay"; |
| |
| pinctrl-0 = <&uart0_pins>; |
| pinctrl-names = "default"; |
| }; |
| |
| /* eMMC */ |
| &ap_sdhci0 { |
| status = "okay"; |
| |
| bus-width = <4>; |
| non-removable; |
| /delete-property/ marvell,xenon-phy-slow-mode; |
| no-1-8-v; |
| }; |
| |
| &cp0_pinctrl { |
| cp0_uart0_pins: cp0-uart0-pins { |
| marvell,pins = "mpp6", "mpp7"; |
| marvell,function = "uart0"; |
| }; |
| |
| cp0_spi0_pins: cp0-spi0-pins { |
| marvell,pins = "mpp56", "mpp57", "mpp58", "mpp59"; |
| marvell,function = "spi0"; |
| }; |
| |
| cp0_spi1_pins: cp0-spi1-pins { |
| marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16"; |
| marvell,function = "spi1"; |
| }; |
| |
| cp0_i2c0_pins: cp0-i2c0-pins { |
| marvell,pins = "mpp37", "mpp38"; |
| marvell,function = "i2c0"; |
| }; |
| |
| cp0_i2c1_pins: cp0-i2c1-pins { |
| marvell,pins = "mpp2", "mpp3"; |
| marvell,function = "i2c1"; |
| }; |
| |
| pca9554_int_pins: pca9554-int-pins { |
| marvell,pins = "mpp27"; |
| marvell,function = "gpio"; |
| }; |
| |
| cp0_rgmii1_pins: cp0-rgmii1-pins { |
| marvell,pins = "mpp44", "mpp45", "mpp46", "mpp47", "mpp48", "mpp49", |
| "mpp50", "mpp51", "mpp52", "mpp53", "mpp54", "mpp55"; |
| marvell,function = "ge1"; |
| }; |
| |
| is31_sdb_pins: is31-sdb-pins { |
| marvell,pins = "mpp30"; |
| marvell,function = "gpio"; |
| }; |
| |
| cp0_pcie_reset_pins: cp0-pcie-reset-pins { |
| marvell,pins = "mpp9"; |
| marvell,function = "gpio"; |
| }; |
| |
| cp0_pcie_clkreq_pins: cp0-pcie-clkreq-pins { |
| marvell,pins = "mpp5"; |
| marvell,function = "pcie1"; |
| }; |
| |
| cp0_switch_pins: cp0-switch-pins { |
| marvell,pins = "mpp0", "mpp1"; |
| marvell,function = "gpio"; |
| }; |
| |
| cp0_phy_pins: cp0-phy-pins { |
| marvell,pins = "mpp12"; |
| marvell,function = "gpio"; |
| }; |
| }; |
| |
| /* mikroBUS UART */ |
| &cp0_uart0 { |
| status = "okay"; |
| |
| pinctrl-names = "default"; |
| pinctrl-0 = <&cp0_uart0_pins>; |
| }; |
| |
| /* mikroBUS SPI */ |
| &cp0_spi0 { |
| status = "okay"; |
| |
| pinctrl-names = "default"; |
| pinctrl-0 = <&cp0_spi0_pins>; |
| }; |
| |
| /* SPI-NOR */ |
| &cp0_spi1{ |
| status = "okay"; |
| |
| pinctrl-names = "default"; |
| pinctrl-0 = <&cp0_spi1_pins>; |
| |
| spi-flash@0 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "jedec,spi-nor"; |
| reg = <0>; |
| spi-max-frequency = <20000000>; |
| |
| partitions { |
| compatible = "fixed-partitions"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| partition@0 { |
| label = "firmware"; |
| reg = <0x0 0x3e0000>; |
| read-only; |
| }; |
| |
| partition@3e0000 { |
| label = "hw-info"; |
| reg = <0x3e0000 0x10000>; |
| read-only; |
| }; |
| |
| partition@3f0000 { |
| label = "u-boot-env"; |
| reg = <0x3f0000 0x10000>; |
| }; |
| }; |
| }; |
| }; |
| |
| /* mikroBUS, 1G SFP and GPIO expander */ |
| &cp0_i2c0 { |
| status = "okay"; |
| |
| pinctrl-names = "default"; |
| pinctrl-0 = <&cp0_i2c0_pins>; |
| clock-frequency = <100000>; |
| |
| sfp_gpio: pca9554@39 { |
| compatible = "nxp,pca9554"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pca9554_int_pins>; |
| reg = <0x39>; |
| |
| interrupt-parent = <&cp0_gpio1>; |
| interrupts = <27 IRQ_TYPE_LEVEL_LOW>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| |
| gpio-controller; |
| #gpio-cells = <2>; |
| |
| /* |
| * IO0_0: SFP+_TX_FAULT |
| * IO0_1: SFP+_TX_DISABLE |
| * IO0_2: SFP+_PRSNT |
| * IO0_3: SFP+_LOSS |
| * IO0_4: SFP_TX_FAULT |
| * IO0_5: SFP_TX_DISABLE |
| * IO0_6: SFP_PRSNT |
| * IO0_7: SFP_LOSS |
| */ |
| }; |
| }; |
| |
| /* IS31FL3199, mini-PCIe and 10G SFP+ */ |
| &cp0_i2c1 { |
| status = "okay"; |
| |
| pinctrl-names = "default"; |
| pinctrl-0 = <&cp0_i2c1_pins>; |
| clock-frequency = <100000>; |
| |
| leds@64 { |
| compatible = "issi,is31fl3199"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&is31_sdb_pins>; |
| shutdown-gpios = <&cp0_gpio1 30 GPIO_ACTIVE_HIGH>; |
| reg = <0x64>; |
| |
| led1_red: led@1 { |
| label = "red:led1"; |
| reg = <1>; |
| led-max-microamp = <20000>; |
| }; |
| |
| led1_green: led@2 { |
| label = "green:led1"; |
| reg = <2>; |
| }; |
| |
| led1_blue: led@3 { |
| label = "blue:led1"; |
| reg = <3>; |
| }; |
| |
| led2_red: led@4 { |
| label = "red:led2"; |
| reg = <4>; |
| }; |
| |
| led2_green: led@5 { |
| label = "green:led2"; |
| reg = <5>; |
| }; |
| |
| led2_blue: led@6 { |
| label = "blue:led2"; |
| reg = <6>; |
| }; |
| |
| led3_red: led@7 { |
| label = "red:led3"; |
| reg = <7>; |
| }; |
| |
| led3_green: led@8 { |
| label = "green:led3"; |
| reg = <8>; |
| }; |
| |
| led3_blue: led@9 { |
| label = "blue:led3"; |
| reg = <9>; |
| }; |
| }; |
| }; |
| |
| &cp0_mdio { |
| status = "okay"; |
| |
| /* 88E1512 PHY */ |
| eth2phy: ethernet-phy@1 { |
| reg = <1>; |
| sfp = <&sfp_eth2>; |
| |
| pinctrl-names = "default"; |
| pinctrl-0 = <&cp0_phy_pins>; |
| reset-gpios = <&cp0_gpio1 12 GPIO_ACTIVE_LOW>; |
| }; |
| |
| /* 88E6141 Topaz switch */ |
| switch: switch@3 { |
| compatible = "marvell,mv88e6085"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <3>; |
| |
| pinctrl-names = "default"; |
| pinctrl-0 = <&cp0_switch_pins>; |
| reset-gpios = <&cp0_gpio1 0 GPIO_ACTIVE_LOW>; |
| |
| interrupt-parent = <&cp0_gpio1>; |
| interrupts = <1 IRQ_TYPE_LEVEL_LOW>; |
| |
| ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| swport1: port@1 { |
| reg = <1>; |
| label = "lan0"; |
| phy-handle = <&swphy1>; |
| }; |
| |
| swport2: port@2 { |
| reg = <2>; |
| label = "lan1"; |
| phy-handle = <&swphy2>; |
| }; |
| |
| swport3: port@3 { |
| reg = <3>; |
| label = "lan2"; |
| phy-handle = <&swphy3>; |
| }; |
| |
| swport4: port@4 { |
| reg = <4>; |
| label = "lan3"; |
| phy-handle = <&swphy4>; |
| }; |
| |
| port@5 { |
| reg = <5>; |
| label = "cpu"; |
| ethernet = <&cp0_eth1>; |
| phy-mode = "2500base-x"; |
| managed = "in-band-status"; |
| }; |
| }; |
| |
| mdio { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| swphy1: swphy1@17 { |
| reg = <17>; |
| }; |
| |
| swphy2: swphy2@18 { |
| reg = <18>; |
| }; |
| |
| swphy3: swphy3@19 { |
| reg = <19>; |
| }; |
| |
| swphy4: swphy4@20 { |
| reg = <20>; |
| }; |
| }; |
| }; |
| }; |
| |
| &cp0_ethernet { |
| status = "okay"; |
| }; |
| |
| /* 10G SFP+ */ |
| &cp0_eth0 { |
| status = "okay"; |
| |
| phy-mode = "10gbase-r"; |
| phys = <&cp0_comphy4 0>; |
| managed = "in-band-status"; |
| sfp = <&sfp_eth0>; |
| }; |
| |
| /* Topaz switch uplink */ |
| &cp0_eth1 { |
| status = "okay"; |
| |
| phy-mode = "2500base-x"; |
| phys = <&cp0_comphy0 1>; |
| |
| fixed-link { |
| speed = <2500>; |
| full-duplex; |
| }; |
| }; |
| |
| /* 1G SFP or 1G RJ45 */ |
| &cp0_eth2 { |
| status = "okay"; |
| |
| pinctrl-names = "default"; |
| pinctrl-0 = <&cp0_rgmii1_pins>; |
| |
| phy = <ð2phy>; |
| phy-mode = "rgmii-id"; |
| }; |
| |
| &cp0_utmi { |
| status = "okay"; |
| }; |
| |
| /* SMSC USB5434B hub */ |
| &cp0_usb3_0 { |
| status = "okay"; |
| |
| phys = <&cp0_comphy1 0>, <&cp0_utmi0>; |
| phy-names = "cp0-usb3h0-comphy", "utmi"; |
| }; |
| |
| /* miniPCI-E USB */ |
| &cp0_usb3_1 { |
| status = "okay"; |
| }; |
| |
| &cp0_sata0 { |
| status = "okay"; |
| |
| /* 7 + 12 SATA connector (J24) */ |
| sata-port@0 { |
| phys = <&cp0_comphy2 0>; |
| phy-names = "cp0-sata0-0-phy"; |
| }; |
| |
| /* M.2-2250 B-key (J39) */ |
| sata-port@1 { |
| phys = <&cp0_comphy3 1>; |
| phy-names = "cp0-sata0-1-phy"; |
| }; |
| }; |
| |
| /* miniPCI-E (J5) */ |
| &cp0_pcie2 { |
| status = "okay"; |
| |
| pinctrl-names = "default", "clkreq"; |
| pinctrl-0 = <&cp0_pcie_reset_pins>; |
| pinctrl-1 = <&cp0_pcie_clkreq_pins>; |
| phys = <&cp0_comphy5 2>; |
| phy-names = "cp0-pcie2-x1-phy"; |
| reset-gpios = <&cp0_gpio1 9 GPIO_ACTIVE_LOW>; |
| }; |
