| // SPDX-License-Identifier: GPL-2.0 |
| /* |
| * Device Tree Source for J7200 SoC Family Main Domain peripherals |
| * |
| * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ |
| */ |
| |
| / { |
| serdes_refclk: serdes-refclk { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| }; |
| }; |
| |
| &cbass_main { |
| msmc_ram: sram@70000000 { |
| compatible = "mmio-sram"; |
| reg = <0x00 0x70000000 0x00 0x100000>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x00 0x00 0x70000000 0x100000>; |
| |
| atf-sram@0 { |
| reg = <0x00 0x20000>; |
| }; |
| }; |
| |
| scm_conf: scm-conf@100000 { |
| compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; |
| reg = <0x00 0x00100000 0x00 0x1c000>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x00 0x00 0x00100000 0x1c000>; |
| |
| serdes_ln_ctrl: serdes-ln-ctrl@4080 { |
| compatible = "mmio-mux"; |
| #mux-control-cells = <1>; |
| mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ |
| <0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */ |
| }; |
| |
| usb_serdes_mux: mux-controller@4000 { |
| compatible = "mmio-mux"; |
| #mux-control-cells = <1>; |
| mux-reg-masks = <0x4000 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ |
| }; |
| }; |
| |
| gic500: interrupt-controller@1800000 { |
| compatible = "arm,gic-v3"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| #interrupt-cells = <3>; |
| interrupt-controller; |
| reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ |
| <0x00 0x01900000 0x00 0x100000>; /* GICR */ |
| |
| /* vcpumntirq: virtual CPU interface maintenance interrupt */ |
| interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| |
| gic_its: msi-controller@1820000 { |
| compatible = "arm,gic-v3-its"; |
| reg = <0x00 0x01820000 0x00 0x10000>; |
| socionext,synquacer-pre-its = <0x1000000 0x400000>; |
| msi-controller; |
| #msi-cells = <1>; |
| }; |
| }; |
| |
| main_gpio_intr: interrupt-controller@a00000 { |
| compatible = "ti,sci-intr"; |
| reg = <0x00 0x00a00000 0x00 0x800>; |
| ti,intr-trigger-type = <1>; |
| interrupt-controller; |
| interrupt-parent = <&gic500>; |
| #interrupt-cells = <1>; |
| ti,sci = <&dmsc>; |
| ti,sci-dev-id = <131>; |
| ti,interrupt-ranges = <8 392 56>; |
| }; |
| |
| main_navss: bus@30000000 { |
| compatible = "simple-mfd"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; |
| ti,sci-dev-id = <199>; |
| dma-coherent; |
| dma-ranges; |
| |
| main_navss_intr: interrupt-controller@310e0000 { |
| compatible = "ti,sci-intr"; |
| reg = <0x00 0x310e0000 0x00 0x4000>; |
| ti,intr-trigger-type = <4>; |
| interrupt-controller; |
| interrupt-parent = <&gic500>; |
| #interrupt-cells = <1>; |
| ti,sci = <&dmsc>; |
| ti,sci-dev-id = <213>; |
| ti,interrupt-ranges = <0 64 64>, |
| <64 448 64>, |
| <128 672 64>; |
| }; |
| |
| main_udmass_inta: msi-controller@33d00000 { |
| compatible = "ti,sci-inta"; |
| reg = <0x00 0x33d00000 0x00 0x100000>; |
| interrupt-controller; |
| #interrupt-cells = <0>; |
| interrupt-parent = <&main_navss_intr>; |
| msi-controller; |
| ti,sci = <&dmsc>; |
| ti,sci-dev-id = <209>; |
| ti,interrupt-ranges = <0 0 256>; |
| }; |
| |
| secure_proxy_main: mailbox@32c00000 { |
| compatible = "ti,am654-secure-proxy"; |
| #mbox-cells = <1>; |
| reg-names = "target_data", "rt", "scfg"; |
| reg = <0x00 0x32c00000 0x00 0x100000>, |
| <0x00 0x32400000 0x00 0x100000>, |
| <0x00 0x32800000 0x00 0x100000>; |
| interrupt-names = "rx_011"; |
| interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| hwspinlock: spinlock@30e00000 { |
| compatible = "ti,am654-hwspinlock"; |
| reg = <0x00 0x30e00000 0x00 0x1000>; |
| #hwlock-cells = <1>; |
| }; |
| |
| mailbox0_cluster0: mailbox@31f80000 { |
| compatible = "ti,am654-mailbox"; |
| reg = <0x00 0x31f80000 0x00 0x200>; |
| #mbox-cells = <1>; |
| ti,mbox-num-users = <4>; |
| ti,mbox-num-fifos = <16>; |
| interrupt-parent = <&main_navss_intr>; |
| }; |
| |
| mailbox0_cluster1: mailbox@31f81000 { |
| compatible = "ti,am654-mailbox"; |
| reg = <0x00 0x31f81000 0x00 0x200>; |
| #mbox-cells = <1>; |
| ti,mbox-num-users = <4>; |
| ti,mbox-num-fifos = <16>; |
| interrupt-parent = <&main_navss_intr>; |
| }; |
| |
| mailbox0_cluster2: mailbox@31f82000 { |
| compatible = "ti,am654-mailbox"; |
| reg = <0x00 0x31f82000 0x00 0x200>; |
| #mbox-cells = <1>; |
| ti,mbox-num-users = <4>; |
| ti,mbox-num-fifos = <16>; |
| interrupt-parent = <&main_navss_intr>; |
| }; |
| |
| mailbox0_cluster3: mailbox@31f83000 { |
| compatible = "ti,am654-mailbox"; |
| reg = <0x00 0x31f83000 0x00 0x200>; |
| #mbox-cells = <1>; |
| ti,mbox-num-users = <4>; |
| ti,mbox-num-fifos = <16>; |
| interrupt-parent = <&main_navss_intr>; |
| }; |
| |
| mailbox0_cluster4: mailbox@31f84000 { |
| compatible = "ti,am654-mailbox"; |
| reg = <0x00 0x31f84000 0x00 0x200>; |
| #mbox-cells = <1>; |
| ti,mbox-num-users = <4>; |
| ti,mbox-num-fifos = <16>; |
| interrupt-parent = <&main_navss_intr>; |
| }; |
| |
| mailbox0_cluster5: mailbox@31f85000 { |
| compatible = "ti,am654-mailbox"; |
| reg = <0x00 0x31f85000 0x00 0x200>; |
| #mbox-cells = <1>; |
| ti,mbox-num-users = <4>; |
| ti,mbox-num-fifos = <16>; |
| interrupt-parent = <&main_navss_intr>; |
| }; |
| |
| mailbox0_cluster6: mailbox@31f86000 { |
| compatible = "ti,am654-mailbox"; |
| reg = <0x00 0x31f86000 0x00 0x200>; |
| #mbox-cells = <1>; |
| ti,mbox-num-users = <4>; |
| ti,mbox-num-fifos = <16>; |
| interrupt-parent = <&main_navss_intr>; |
| }; |
| |
| mailbox0_cluster7: mailbox@31f87000 { |
| compatible = "ti,am654-mailbox"; |
| reg = <0x00 0x31f87000 0x00 0x200>; |
| #mbox-cells = <1>; |
| ti,mbox-num-users = <4>; |
| ti,mbox-num-fifos = <16>; |
| interrupt-parent = <&main_navss_intr>; |
| }; |
| |
| mailbox0_cluster8: mailbox@31f88000 { |
| compatible = "ti,am654-mailbox"; |
| reg = <0x00 0x31f88000 0x00 0x200>; |
| #mbox-cells = <1>; |
| ti,mbox-num-users = <4>; |
| ti,mbox-num-fifos = <16>; |
| interrupt-parent = <&main_navss_intr>; |
| }; |
| |
| mailbox0_cluster9: mailbox@31f89000 { |
| compatible = "ti,am654-mailbox"; |
| reg = <0x00 0x31f89000 0x00 0x200>; |
| #mbox-cells = <1>; |
| ti,mbox-num-users = <4>; |
| ti,mbox-num-fifos = <16>; |
| interrupt-parent = <&main_navss_intr>; |
| }; |
| |
| mailbox0_cluster10: mailbox@31f8a000 { |
| compatible = "ti,am654-mailbox"; |
| reg = <0x00 0x31f8a000 0x00 0x200>; |
| #mbox-cells = <1>; |
| ti,mbox-num-users = <4>; |
| ti,mbox-num-fifos = <16>; |
| interrupt-parent = <&main_navss_intr>; |
| }; |
| |
| mailbox0_cluster11: mailbox@31f8b000 { |
| compatible = "ti,am654-mailbox"; |
| reg = <0x00 0x31f8b000 0x00 0x200>; |
| #mbox-cells = <1>; |
| ti,mbox-num-users = <4>; |
| ti,mbox-num-fifos = <16>; |
| interrupt-parent = <&main_navss_intr>; |
| }; |
| |
| main_ringacc: ringacc@3c000000 { |
| compatible = "ti,am654-navss-ringacc"; |
| reg = <0x00 0x3c000000 0x00 0x400000>, |
| <0x00 0x38000000 0x00 0x400000>, |
| <0x00 0x31120000 0x00 0x100>, |
| <0x00 0x33000000 0x00 0x40000>; |
| reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; |
| ti,num-rings = <1024>; |
| ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ |
| ti,sci = <&dmsc>; |
| ti,sci-dev-id = <211>; |
| msi-parent = <&main_udmass_inta>; |
| }; |
| |
| main_udmap: dma-controller@31150000 { |
| compatible = "ti,j721e-navss-main-udmap"; |
| reg = <0x00 0x31150000 0x00 0x100>, |
| <0x00 0x34000000 0x00 0x100000>, |
| <0x00 0x35000000 0x00 0x100000>; |
| reg-names = "gcfg", "rchanrt", "tchanrt"; |
| msi-parent = <&main_udmass_inta>; |
| #dma-cells = <1>; |
| |
| ti,sci = <&dmsc>; |
| ti,sci-dev-id = <212>; |
| ti,ringacc = <&main_ringacc>; |
| |
| ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ |
| <0x0f>, /* TX_HCHAN */ |
| <0x10>; /* TX_UHCHAN */ |
| ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ |
| <0x0b>, /* RX_HCHAN */ |
| <0x0c>; /* RX_UHCHAN */ |
| ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ |
| }; |
| |
| cpts@310d0000 { |
| compatible = "ti,j721e-cpts"; |
| reg = <0x00 0x310d0000 0x00 0x400>; |
| reg-names = "cpts"; |
| clocks = <&k3_clks 201 1>; |
| clock-names = "cpts"; |
| interrupts-extended = <&main_navss_intr 391>; |
| interrupt-names = "cpts"; |
| ti,cpts-periodic-outputs = <6>; |
| ti,cpts-ext-ts-inputs = <8>; |
| }; |
| }; |
| |
| main_pmx0: pinctrl@11c000 { |
| compatible = "pinctrl-single"; |
| /* Proxy 0 addressing */ |
| reg = <0x00 0x11c000 0x00 0x2b4>; |
| #pinctrl-cells = <1>; |
| pinctrl-single,register-width = <32>; |
| pinctrl-single,function-mask = <0xffffffff>; |
| }; |
| |
| main_uart0: serial@2800000 { |
| compatible = "ti,j721e-uart", "ti,am654-uart"; |
| reg = <0x00 0x02800000 0x00 0x100>; |
| interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; |
| clock-frequency = <48000000>; |
| current-speed = <115200>; |
| power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 146 2>; |
| clock-names = "fclk"; |
| }; |
| |
| main_uart1: serial@2810000 { |
| compatible = "ti,j721e-uart", "ti,am654-uart"; |
| reg = <0x00 0x02810000 0x00 0x100>; |
| interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; |
| clock-frequency = <48000000>; |
| current-speed = <115200>; |
| power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 278 2>; |
| clock-names = "fclk"; |
| }; |
| |
| main_uart2: serial@2820000 { |
| compatible = "ti,j721e-uart", "ti,am654-uart"; |
| reg = <0x00 0x02820000 0x00 0x100>; |
| interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; |
| clock-frequency = <48000000>; |
| current-speed = <115200>; |
| power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 279 2>; |
| clock-names = "fclk"; |
| }; |
| |
| main_uart3: serial@2830000 { |
| compatible = "ti,j721e-uart", "ti,am654-uart"; |
| reg = <0x00 0x02830000 0x00 0x100>; |
| interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; |
| clock-frequency = <48000000>; |
| current-speed = <115200>; |
| power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 280 2>; |
| clock-names = "fclk"; |
| }; |
| |
| main_uart4: serial@2840000 { |
| compatible = "ti,j721e-uart", "ti,am654-uart"; |
| reg = <0x00 0x02840000 0x00 0x100>; |
| interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; |
| clock-frequency = <48000000>; |
| current-speed = <115200>; |
| power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 281 2>; |
| clock-names = "fclk"; |
| }; |
| |
| main_uart5: serial@2850000 { |
| compatible = "ti,j721e-uart", "ti,am654-uart"; |
| reg = <0x00 0x02850000 0x00 0x100>; |
| interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; |
| clock-frequency = <48000000>; |
| current-speed = <115200>; |
| power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 282 2>; |
| clock-names = "fclk"; |
| }; |
| |
| main_uart6: serial@2860000 { |
| compatible = "ti,j721e-uart", "ti,am654-uart"; |
| reg = <0x00 0x02860000 0x00 0x100>; |
| interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; |
| clock-frequency = <48000000>; |
| current-speed = <115200>; |
| power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 283 2>; |
| clock-names = "fclk"; |
| }; |
| |
| main_uart7: serial@2870000 { |
| compatible = "ti,j721e-uart", "ti,am654-uart"; |
| reg = <0x00 0x02870000 0x00 0x100>; |
| interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; |
| clock-frequency = <48000000>; |
| current-speed = <115200>; |
| power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 284 2>; |
| clock-names = "fclk"; |
| }; |
| |
| main_uart8: serial@2880000 { |
| compatible = "ti,j721e-uart", "ti,am654-uart"; |
| reg = <0x00 0x02880000 0x00 0x100>; |
| interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; |
| clock-frequency = <48000000>; |
| current-speed = <115200>; |
| power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 285 2>; |
| clock-names = "fclk"; |
| }; |
| |
| main_uart9: serial@2890000 { |
| compatible = "ti,j721e-uart", "ti,am654-uart"; |
| reg = <0x00 0x02890000 0x00 0x100>; |
| interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; |
| clock-frequency = <48000000>; |
| current-speed = <115200>; |
| power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 286 2>; |
| clock-names = "fclk"; |
| }; |
| |
| main_i2c0: i2c@2000000 { |
| compatible = "ti,j721e-i2c", "ti,omap4-i2c"; |
| reg = <0x00 0x2000000 0x00 0x100>; |
| interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clock-names = "fck"; |
| clocks = <&k3_clks 187 1>; |
| power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>; |
| }; |
| |
| main_i2c1: i2c@2010000 { |
| compatible = "ti,j721e-i2c", "ti,omap4-i2c"; |
| reg = <0x00 0x2010000 0x00 0x100>; |
| interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clock-names = "fck"; |
| clocks = <&k3_clks 188 1>; |
| power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; |
| }; |
| |
| main_i2c2: i2c@2020000 { |
| compatible = "ti,j721e-i2c", "ti,omap4-i2c"; |
| reg = <0x00 0x2020000 0x00 0x100>; |
| interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clock-names = "fck"; |
| clocks = <&k3_clks 189 1>; |
| power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; |
| }; |
| |
| main_i2c3: i2c@2030000 { |
| compatible = "ti,j721e-i2c", "ti,omap4-i2c"; |
| reg = <0x00 0x2030000 0x00 0x100>; |
| interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clock-names = "fck"; |
| clocks = <&k3_clks 190 1>; |
| power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; |
| }; |
| |
| main_i2c4: i2c@2040000 { |
| compatible = "ti,j721e-i2c", "ti,omap4-i2c"; |
| reg = <0x00 0x2040000 0x00 0x100>; |
| interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clock-names = "fck"; |
| clocks = <&k3_clks 191 1>; |
| power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; |
| }; |
| |
| main_i2c5: i2c@2050000 { |
| compatible = "ti,j721e-i2c", "ti,omap4-i2c"; |
| reg = <0x00 0x2050000 0x00 0x100>; |
| interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clock-names = "fck"; |
| clocks = <&k3_clks 192 1>; |
| power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; |
| }; |
| |
| main_i2c6: i2c@2060000 { |
| compatible = "ti,j721e-i2c", "ti,omap4-i2c"; |
| reg = <0x00 0x2060000 0x00 0x100>; |
| interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clock-names = "fck"; |
| clocks = <&k3_clks 193 1>; |
| power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; |
| }; |
| |
| main_sdhci0: mmc@4f80000 { |
| compatible = "ti,j7200-sdhci-8bit", "ti,j721e-sdhci-8bit"; |
| reg = <0x00 0x04f80000 0x00 0x260>, <0x00 0x4f88000 0x00 0x134>; |
| interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; |
| clock-names = "clk_ahb", "clk_xin"; |
| clocks = <&k3_clks 91 0>, <&k3_clks 91 3>; |
| ti,otap-del-sel-legacy = <0x0>; |
| ti,otap-del-sel-mmc-hs = <0x0>; |
| ti,otap-del-sel-ddr52 = <0x6>; |
| ti,otap-del-sel-hs200 = <0x8>; |
| ti,otap-del-sel-hs400 = <0x5>; |
| ti,itap-del-sel-legacy = <0x10>; |
| ti,itap-del-sel-mmc-hs = <0xa>; |
| ti,strobe-sel = <0x77>; |
| ti,clkbuf-sel = <0x7>; |
| ti,trm-icp = <0x8>; |
| bus-width = <8>; |
| mmc-ddr-1_8v; |
| mmc-hs200-1_8v; |
| mmc-hs400-1_8v; |
| dma-coherent; |
| }; |
| |
| main_sdhci1: mmc@4fb0000 { |
| compatible = "ti,j7200-sdhci-4bit", "ti,j721e-sdhci-4bit"; |
| reg = <0x00 0x04fb0000 0x00 0x260>, <0x00 0x4fb8000 0x00 0x134>; |
| interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; |
| clock-names = "clk_ahb", "clk_xin"; |
| clocks = <&k3_clks 92 1>, <&k3_clks 92 2>; |
| ti,otap-del-sel-legacy = <0x0>; |
| ti,otap-del-sel-sd-hs = <0x0>; |
| ti,otap-del-sel-sdr12 = <0xf>; |
| ti,otap-del-sel-sdr25 = <0xf>; |
| ti,otap-del-sel-sdr50 = <0xc>; |
| ti,otap-del-sel-sdr104 = <0x5>; |
| ti,otap-del-sel-ddr50 = <0xc>; |
| ti,itap-del-sel-legacy = <0x0>; |
| ti,itap-del-sel-sd-hs = <0x0>; |
| ti,itap-del-sel-sdr12 = <0x0>; |
| ti,itap-del-sel-sdr25 = <0x0>; |
| ti,clkbuf-sel = <0x7>; |
| ti,trm-icp = <0x8>; |
| dma-coherent; |
| }; |
| |
| serdes_wiz0: wiz@5060000 { |
| compatible = "ti,j721e-wiz-10g"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 292 11>, <&k3_clks 292 85>, <&serdes_refclk>; |
| clock-names = "fck", "core_ref_clk", "ext_ref_clk"; |
| num-lanes = <4>; |
| #reset-cells = <1>; |
| ranges = <0x5060000 0x0 0x5060000 0x10000>; |
| |
| assigned-clocks = <&k3_clks 292 85>; |
| assigned-clock-parents = <&k3_clks 292 89>; |
| |
| wiz0_pll0_refclk: pll0-refclk { |
| clocks = <&k3_clks 292 85>, <&serdes_refclk>; |
| clock-output-names = "wiz0_pll0_refclk"; |
| #clock-cells = <0>; |
| assigned-clocks = <&wiz0_pll0_refclk>; |
| assigned-clock-parents = <&k3_clks 292 85>; |
| }; |
| |
| wiz0_pll1_refclk: pll1-refclk { |
| clocks = <&k3_clks 292 85>, <&serdes_refclk>; |
| clock-output-names = "wiz0_pll1_refclk"; |
| #clock-cells = <0>; |
| assigned-clocks = <&wiz0_pll1_refclk>; |
| assigned-clock-parents = <&k3_clks 292 85>; |
| }; |
| |
| wiz0_refclk_dig: refclk-dig { |
| clocks = <&k3_clks 292 85>, <&serdes_refclk>; |
| clock-output-names = "wiz0_refclk_dig"; |
| #clock-cells = <0>; |
| assigned-clocks = <&wiz0_refclk_dig>; |
| assigned-clock-parents = <&k3_clks 292 85>; |
| }; |
| |
| wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div { |
| clocks = <&wiz0_refclk_dig>; |
| #clock-cells = <0>; |
| }; |
| |
| serdes0: serdes@5060000 { |
| compatible = "ti,j721e-serdes-10g"; |
| reg = <0x05060000 0x00010000>; |
| reg-names = "torrent_phy"; |
| resets = <&serdes_wiz0 0>; |
| reset-names = "torrent_reset"; |
| clocks = <&wiz0_pll0_refclk>; |
| clock-names = "refclk"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| }; |
| |
| pcie1_rc: pcie@2910000 { |
| compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host"; |
| reg = <0x00 0x02910000 0x00 0x1000>, |
| <0x00 0x02917000 0x00 0x400>, |
| <0x00 0x0d800000 0x00 0x00800000>, |
| <0x00 0x18000000 0x00 0x00001000>; |
| reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; |
| interrupt-names = "link_state"; |
| interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; |
| device_type = "pci"; |
| ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; |
| max-link-speed = <3>; |
| num-lanes = <4>; |
| power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 240 6>; |
| clock-names = "fck"; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| bus-range = <0x0 0xff>; |
| cdns,no-bar-match-nbits = <64>; |
| vendor-id = <0x104c>; |
| device-id = <0xb00f>; |
| msi-map = <0x0 &gic_its 0x0 0x10000>; |
| dma-coherent; |
| ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, |
| <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; |
| dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; |
| }; |
| |
| pcie1_ep: pcie-ep@2910000 { |
| compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep"; |
| reg = <0x00 0x02910000 0x00 0x1000>, |
| <0x00 0x02917000 0x00 0x400>, |
| <0x00 0x0d800000 0x00 0x00800000>, |
| <0x00 0x18000000 0x00 0x08000000>; |
| reg-names = "intd_cfg", "user_cfg", "reg", "mem"; |
| interrupt-names = "link_state"; |
| interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; |
| ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; |
| max-link-speed = <3>; |
| num-lanes = <4>; |
| power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 240 6>; |
| clock-names = "fck"; |
| max-functions = /bits/ 8 <6>; |
| max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; |
| dma-coherent; |
| }; |
| |
| usbss0: cdns-usb@4104000 { |
| compatible = "ti,j721e-usb"; |
| reg = <0x00 0x4104000 0x00 0x100>; |
| dma-coherent; |
| power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 288 12>, <&k3_clks 288 3>; |
| clock-names = "ref", "lpm"; |
| assigned-clocks = <&k3_clks 288 12>; /* USB2_REFCLK */ |
| assigned-clock-parents = <&k3_clks 288 13>; /* HFOSC0 */ |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| usb0: usb@6000000 { |
| compatible = "cdns,usb3"; |
| reg = <0x00 0x6000000 0x00 0x10000>, |
| <0x00 0x6010000 0x00 0x10000>, |
| <0x00 0x6020000 0x00 0x10000>; |
| reg-names = "otg", "xhci", "dev"; |
| interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ |
| <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ |
| <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ |
| interrupt-names = "host", |
| "peripheral", |
| "otg"; |
| maximum-speed = "super-speed"; |
| dr_mode = "otg"; |
| cdns,phyrst-a-enable; |
| }; |
| }; |
| |
| main_gpio0: gpio@600000 { |
| compatible = "ti,j721e-gpio", "ti,keystone-gpio"; |
| reg = <0x00 0x00600000 0x00 0x100>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-parent = <&main_gpio_intr>; |
| interrupts = <145>, <146>, <147>, <148>, |
| <149>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| ti,ngpio = <69>; |
| ti,davinci-gpio-unbanked = <0>; |
| power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 105 0>; |
| clock-names = "gpio"; |
| }; |
| |
| main_gpio2: gpio@610000 { |
| compatible = "ti,j721e-gpio", "ti,keystone-gpio"; |
| reg = <0x00 0x00610000 0x00 0x100>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-parent = <&main_gpio_intr>; |
| interrupts = <154>, <155>, <156>, <157>, |
| <158>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| ti,ngpio = <69>; |
| ti,davinci-gpio-unbanked = <0>; |
| power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 107 0>; |
| clock-names = "gpio"; |
| }; |
| |
| main_gpio4: gpio@620000 { |
| compatible = "ti,j721e-gpio", "ti,keystone-gpio"; |
| reg = <0x00 0x00620000 0x00 0x100>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-parent = <&main_gpio_intr>; |
| interrupts = <163>, <164>, <165>, <166>, |
| <167>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| ti,ngpio = <69>; |
| ti,davinci-gpio-unbanked = <0>; |
| power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 109 0>; |
| clock-names = "gpio"; |
| }; |
| |
| main_gpio6: gpio@630000 { |
| compatible = "ti,j721e-gpio", "ti,keystone-gpio"; |
| reg = <0x00 0x00630000 0x00 0x100>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-parent = <&main_gpio_intr>; |
| interrupts = <172>, <173>, <174>, <175>, |
| <176>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| ti,ngpio = <69>; |
| ti,davinci-gpio-unbanked = <0>; |
| power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 111 0>; |
| clock-names = "gpio"; |
| }; |
| |
| main_r5fss0: r5fss@5c00000 { |
| compatible = "ti,j7200-r5fss"; |
| ti,cluster-mode = <1>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x5c00000 0x00 0x5c00000 0x20000>, |
| <0x5d00000 0x00 0x5d00000 0x20000>; |
| power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>; |
| |
| main_r5fss0_core0: r5f@5c00000 { |
| compatible = "ti,j7200-r5f"; |
| reg = <0x5c00000 0x00010000>, |
| <0x5c10000 0x00010000>; |
| reg-names = "atcm", "btcm"; |
| ti,sci = <&dmsc>; |
| ti,sci-dev-id = <245>; |
| ti,sci-proc-ids = <0x06 0xff>; |
| resets = <&k3_reset 245 1>; |
| firmware-name = "j7200-main-r5f0_0-fw"; |
| ti,atcm-enable = <1>; |
| ti,btcm-enable = <1>; |
| ti,loczrama = <1>; |
| }; |
| |
| main_r5fss0_core1: r5f@5d00000 { |
| compatible = "ti,j7200-r5f"; |
| reg = <0x5d00000 0x00008000>, |
| <0x5d10000 0x00008000>; |
| reg-names = "atcm", "btcm"; |
| ti,sci = <&dmsc>; |
| ti,sci-dev-id = <246>; |
| ti,sci-proc-ids = <0x07 0xff>; |
| resets = <&k3_reset 246 1>; |
| firmware-name = "j7200-main-r5f0_1-fw"; |
| ti,atcm-enable = <1>; |
| ti,btcm-enable = <1>; |
| ti,loczrama = <1>; |
| }; |
| }; |
| }; |
