| // SPDX-License-Identifier: (GPL-2.0 OR MIT) |
| /* |
| * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org> |
| * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com> |
| */ |
| |
| #include <dt-bindings/clock/sophgo,cv1800.h> |
| #include <dt-bindings/gpio/gpio.h> |
| #include <dt-bindings/interrupt-controller/irq.h> |
| |
| / { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| cpus: cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| timebase-frequency = <25000000>; |
| |
| cpu0: cpu@0 { |
| compatible = "thead,c906", "riscv"; |
| device_type = "cpu"; |
| reg = <0>; |
| d-cache-block-size = <64>; |
| d-cache-sets = <512>; |
| d-cache-size = <65536>; |
| i-cache-block-size = <64>; |
| i-cache-sets = <128>; |
| i-cache-size = <32768>; |
| mmu-type = "riscv,sv39"; |
| riscv,isa = "rv64imafdc"; |
| riscv,isa-base = "rv64i"; |
| riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", |
| "zifencei", "zihpm"; |
| |
| cpu0_intc: interrupt-controller { |
| compatible = "riscv,cpu-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| }; |
| |
| osc: oscillator { |
| compatible = "fixed-clock"; |
| clock-output-names = "osc_25m"; |
| #clock-cells = <0>; |
| }; |
| |
| soc { |
| compatible = "simple-bus"; |
| interrupt-parent = <&plic>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| dma-noncoherent; |
| ranges; |
| |
| clk: clock-controller@3002000 { |
| reg = <0x03002000 0x1000>; |
| clocks = <&osc>; |
| #clock-cells = <1>; |
| }; |
| |
| gpio0: gpio@3020000 { |
| compatible = "snps,dw-apb-gpio"; |
| reg = <0x3020000 0x1000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| porta: gpio-controller@0 { |
| compatible = "snps,dw-apb-gpio-port"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| ngpios = <32>; |
| reg = <0>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| interrupts = <60 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| }; |
| |
| gpio1: gpio@3021000 { |
| compatible = "snps,dw-apb-gpio"; |
| reg = <0x3021000 0x1000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| portb: gpio-controller@0 { |
| compatible = "snps,dw-apb-gpio-port"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| ngpios = <32>; |
| reg = <0>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| interrupts = <61 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| }; |
| |
| gpio2: gpio@3022000 { |
| compatible = "snps,dw-apb-gpio"; |
| reg = <0x3022000 0x1000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| portc: gpio-controller@0 { |
| compatible = "snps,dw-apb-gpio-port"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| ngpios = <32>; |
| reg = <0>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| interrupts = <62 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| }; |
| |
| gpio3: gpio@3023000 { |
| compatible = "snps,dw-apb-gpio"; |
| reg = <0x3023000 0x1000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| portd: gpio-controller@0 { |
| compatible = "snps,dw-apb-gpio-port"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| ngpios = <32>; |
| reg = <0>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| interrupts = <63 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| }; |
| |
| i2c0: i2c@4000000 { |
| compatible = "snps,designware-i2c"; |
| reg = <0x04000000 0x10000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C0>; |
| clock-names = "ref", "pclk"; |
| interrupts = <49 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| }; |
| |
| i2c1: i2c@4010000 { |
| compatible = "snps,designware-i2c"; |
| reg = <0x04010000 0x10000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C1>; |
| clock-names = "ref", "pclk"; |
| interrupts = <50 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| }; |
| |
| i2c2: i2c@4020000 { |
| compatible = "snps,designware-i2c"; |
| reg = <0x04020000 0x10000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C2>; |
| clock-names = "ref", "pclk"; |
| interrupts = <51 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| }; |
| |
| i2c3: i2c@4030000 { |
| compatible = "snps,designware-i2c"; |
| reg = <0x04030000 0x10000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C3>; |
| clock-names = "ref", "pclk"; |
| interrupts = <52 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| }; |
| |
| i2c4: i2c@4040000 { |
| compatible = "snps,designware-i2c"; |
| reg = <0x04040000 0x10000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C4>; |
| clock-names = "ref", "pclk"; |
| interrupts = <53 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| }; |
| |
| uart0: serial@4140000 { |
| compatible = "snps,dw-apb-uart"; |
| reg = <0x04140000 0x100>; |
| interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clk CLK_UART0>, <&clk CLK_APB_UART0>; |
| clock-names = "baudclk", "apb_pclk"; |
| reg-shift = <2>; |
| reg-io-width = <4>; |
| status = "disabled"; |
| }; |
| |
| uart1: serial@4150000 { |
| compatible = "snps,dw-apb-uart"; |
| reg = <0x04150000 0x100>; |
| interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clk CLK_UART1>, <&clk CLK_APB_UART1>; |
| clock-names = "baudclk", "apb_pclk"; |
| reg-shift = <2>; |
| reg-io-width = <4>; |
| status = "disabled"; |
| }; |
| |
| uart2: serial@4160000 { |
| compatible = "snps,dw-apb-uart"; |
| reg = <0x04160000 0x100>; |
| interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clk CLK_UART2>, <&clk CLK_APB_UART2>; |
| clock-names = "baudclk", "apb_pclk"; |
| reg-shift = <2>; |
| reg-io-width = <4>; |
| status = "disabled"; |
| }; |
| |
| uart3: serial@4170000 { |
| compatible = "snps,dw-apb-uart"; |
| reg = <0x04170000 0x100>; |
| interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clk CLK_UART3>, <&clk CLK_APB_UART3>; |
| clock-names = "baudclk", "apb_pclk"; |
| reg-shift = <2>; |
| reg-io-width = <4>; |
| status = "disabled"; |
| }; |
| |
| spi0: spi@4180000 { |
| compatible = "snps,dw-apb-ssi"; |
| reg = <0x04180000 0x10000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI0>; |
| clock-names = "ssi_clk", "pclk"; |
| interrupts = <54 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| }; |
| |
| spi1: spi@4190000 { |
| compatible = "snps,dw-apb-ssi"; |
| reg = <0x04190000 0x10000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI1>; |
| clock-names = "ssi_clk", "pclk"; |
| interrupts = <55 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| }; |
| |
| spi2: spi@41a0000 { |
| compatible = "snps,dw-apb-ssi"; |
| reg = <0x041a0000 0x10000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI2>; |
| clock-names = "ssi_clk", "pclk"; |
| interrupts = <56 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| }; |
| |
| spi3: spi@41b0000 { |
| compatible = "snps,dw-apb-ssi"; |
| reg = <0x041b0000 0x10000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI3>; |
| clock-names = "ssi_clk", "pclk"; |
| interrupts = <57 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| }; |
| |
| uart4: serial@41c0000 { |
| compatible = "snps,dw-apb-uart"; |
| reg = <0x041c0000 0x100>; |
| interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clk CLK_UART4>, <&clk CLK_APB_UART4>; |
| clock-names = "baudclk", "apb_pclk"; |
| reg-shift = <2>; |
| reg-io-width = <4>; |
| status = "disabled"; |
| }; |
| |
| sdhci0: mmc@4310000 { |
| compatible = "sophgo,cv1800b-dwcmshc"; |
| reg = <0x4310000 0x1000>; |
| interrupts = <36 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clk CLK_AXI4_SD0>, |
| <&clk CLK_SD0>; |
| clock-names = "core", "bus"; |
| status = "disabled"; |
| }; |
| |
| dmac: dma-controller@4330000 { |
| compatible = "snps,axi-dma-1.01a"; |
| reg = <0x04330000 0x1000>; |
| interrupts = <29 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clk CLK_SDMA_AXI>, <&clk CLK_SDMA_AXI>; |
| clock-names = "core-clk", "cfgr-clk"; |
| #dma-cells = <1>; |
| dma-channels = <8>; |
| snps,block-size = <1024 1024 1024 1024 |
| 1024 1024 1024 1024>; |
| snps,priority = <0 1 2 3 4 5 6 7>; |
| snps,dma-masters = <2>; |
| snps,data-width = <4>; |
| status = "disabled"; |
| }; |
| |
| plic: interrupt-controller@70000000 { |
| reg = <0x70000000 0x4000000>; |
| interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>; |
| interrupt-controller; |
| #address-cells = <0>; |
| #interrupt-cells = <2>; |
| riscv,ndev = <101>; |
| }; |
| |
| clint: timer@74000000 { |
| reg = <0x74000000 0x10000>; |
| interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>; |
| }; |
| }; |
| }; |
