| /* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ |
| /* |
| * Copyright (c) 2023 Amlogic, Inc. All rights reserved. |
| * Author: Chuan Liu <chuan.liu@amlogic.com> |
| */ |
| |
| #ifndef _DT_BINDINGS_CLOCK_AMLOGIC_C3_PLL_CLKC_H |
| #define _DT_BINDINGS_CLOCK_AMLOGIC_C3_PLL_CLKC_H |
| |
| #define CLKID_FCLK_50M_EN 0 |
| #define CLKID_FCLK_50M 1 |
| #define CLKID_FCLK_DIV2_DIV 2 |
| #define CLKID_FCLK_DIV2 3 |
| #define CLKID_FCLK_DIV2P5_DIV 4 |
| #define CLKID_FCLK_DIV2P5 5 |
| #define CLKID_FCLK_DIV3_DIV 6 |
| #define CLKID_FCLK_DIV3 7 |
| #define CLKID_FCLK_DIV4_DIV 8 |
| #define CLKID_FCLK_DIV4 9 |
| #define CLKID_FCLK_DIV5_DIV 10 |
| #define CLKID_FCLK_DIV5 11 |
| #define CLKID_FCLK_DIV7_DIV 12 |
| #define CLKID_FCLK_DIV7 13 |
| #define CLKID_GP0_PLL_DCO 14 |
| #define CLKID_GP0_PLL 15 |
| #define CLKID_HIFI_PLL_DCO 16 |
| #define CLKID_HIFI_PLL 17 |
| #define CLKID_MCLK_PLL_DCO 18 |
| #define CLKID_MCLK_PLL_OD 19 |
| #define CLKID_MCLK_PLL 20 |
| #define CLKID_MCLK0_SEL 21 |
| #define CLKID_MCLK0_SEL_EN 22 |
| #define CLKID_MCLK0_DIV 23 |
| #define CLKID_MCLK0 24 |
| #define CLKID_MCLK1_SEL 25 |
| #define CLKID_MCLK1_SEL_EN 26 |
| #define CLKID_MCLK1_DIV 27 |
| #define CLKID_MCLK1 28 |
| |
| #endif /* _DT_BINDINGS_CLOCK_AMLOGIC_C3_PLL_CLKC_H */ |
