| Flexcan CAN controller on Freescale's ARM and PowerPC system-on-a-chip (SOC). |
| |
| Required properties: |
| |
| - compatible : Should be "fsl,<processor>-flexcan" |
| |
| where <processor> is imx8qm, imx6q, imx28, imx53, imx35, imx25, p1010, |
| vf610, ls1021ar2, lx2160ar1, ls1028ar1. |
| |
| The ls1028ar1 must be followed by lx2160ar1, e.g. |
| - "fsl,ls1028ar1-flexcan", "fsl,lx2160ar1-flexcan" |
| |
| An implementation should also claim any of the following compatibles |
| that it is fully backwards compatible with: |
| |
| - fsl,p1010-flexcan |
| |
| - reg : Offset and length of the register set for this device |
| - interrupts : Interrupt tuple for this device |
| |
| Optional properties: |
| |
| - clock-frequency : The oscillator frequency driving the flexcan device |
| |
| - xceiver-supply: Regulator that powers the CAN transceiver |
| |
| - big-endian: This means the registers of FlexCAN controller are big endian. |
| This is optional property.i.e. if this property is not present in |
| device tree node then controller is assumed to be little endian. |
| if this property is present then controller is assumed to be big |
| endian. |
| |
| - fsl,stop-mode: register bits of stop mode control, the format is |
| <&gpr req_gpr req_bit>. |
| gpr is the phandle to general purpose register node. |
| req_gpr is the gpr register offset of CAN stop request. |
| req_bit is the bit offset of CAN stop request. |
| |
| - fsl,clk-source: Select the clock source to the CAN Protocol Engine (PE). |
| It's SoC Implementation dependent. Refer to RM for detailed |
| definition. If this property is not set in device tree node |
| then driver selects clock source 1 by default. |
| 0: clock source 0 (oscillator clock) |
| 1: clock source 1 (peripheral clock) |
| |
| - wakeup-source: enable CAN remote wakeup |
| |
| Example: |
| |
| can@1c000 { |
| compatible = "fsl,p1010-flexcan"; |
| reg = <0x1c000 0x1000>; |
| interrupts = <48 0x2>; |
| interrupt-parent = <&mpic>; |
| clock-frequency = <200000000>; // filled in by bootloader |
| fsl,clk-source = <0>; // select clock source 0 for PE |
| }; |