Documentation/devicetree/bindings/timer/jcore,pit.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/jcore,pit.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: J-Core Programmable Interval Timer and Clocksource

maintainers:
  - Rich Felker <dalias@libc.org>

properties:
  compatible:
    const: jcore,pit

  reg:
    description:
      Memory region(s) for timer/clocksource registers. For SMP, there should be
      one region per cpu, indexed by the sequential, zero-based hardware cpu
      number.

  interrupts:
    description:
      An interrupt to assign for the timer. The actual pit core is integrated
      with the aic and allows the timer interrupt assignment to be programmed by
      software, but this property is required in order to reserve an interrupt
      number that doesn't conflict with other devices.
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts

additionalProperties: false

examples:
  - |
    timer@200 {
        compatible = "jcore,pit";
        reg = <0x200 0x30 0x500 0x30>;
        interrupts = <0x48>;
    };