| /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ |
| /* |
| * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. |
| */ |
| |
| #ifndef _DT_BINDINGS_RESET_QCOM_QCA8K_NSS_CC_H |
| #define _DT_BINDINGS_RESET_QCOM_QCA8K_NSS_CC_H |
| |
| #define NSS_CC_SWITCH_CORE_ARES 1 |
| #define NSS_CC_APB_BRIDGE_ARES 2 |
| #define NSS_CC_MAC0_TX_ARES 3 |
| #define NSS_CC_MAC0_TX_SRDS1_ARES 4 |
| #define NSS_CC_MAC0_RX_ARES 5 |
| #define NSS_CC_MAC0_RX_SRDS1_ARES 6 |
| #define NSS_CC_MAC1_SRDS1_CH0_RX_ARES 7 |
| #define NSS_CC_MAC1_TX_ARES 8 |
| #define NSS_CC_MAC1_GEPHY0_TX_ARES 9 |
| #define NSS_CC_MAC1_SRDS1_CH0_XGMII_RX_ARES 10 |
| #define NSS_CC_MAC1_SRDS1_CH0_TX_ARES 11 |
| #define NSS_CC_MAC1_RX_ARES 12 |
| #define NSS_CC_MAC1_GEPHY0_RX_ARES 13 |
| #define NSS_CC_MAC1_SRDS1_CH0_XGMII_TX_ARES 14 |
| #define NSS_CC_MAC2_SRDS1_CH1_RX_ARES 15 |
| #define NSS_CC_MAC2_TX_ARES 16 |
| #define NSS_CC_MAC2_GEPHY1_TX_ARES 17 |
| #define NSS_CC_MAC2_SRDS1_CH1_XGMII_RX_ARES 18 |
| #define NSS_CC_MAC2_SRDS1_CH1_TX_ARES 19 |
| #define NSS_CC_MAC2_RX_ARES 20 |
| #define NSS_CC_MAC2_GEPHY1_RX_ARES 21 |
| #define NSS_CC_MAC2_SRDS1_CH1_XGMII_TX_ARES 22 |
| #define NSS_CC_MAC3_SRDS1_CH2_RX_ARES 23 |
| #define NSS_CC_MAC3_TX_ARES 24 |
| #define NSS_CC_MAC3_GEPHY2_TX_ARES 25 |
| #define NSS_CC_MAC3_SRDS1_CH2_XGMII_RX_ARES 26 |
| #define NSS_CC_MAC3_SRDS1_CH2_TX_ARES 27 |
| #define NSS_CC_MAC3_RX_ARES 28 |
| #define NSS_CC_MAC3_GEPHY2_RX_ARES 29 |
| #define NSS_CC_MAC3_SRDS1_CH2_XGMII_TX_ARES 30 |
| #define NSS_CC_MAC4_SRDS1_CH3_RX_ARES 31 |
| #define NSS_CC_MAC4_TX_ARES 32 |
| #define NSS_CC_MAC4_GEPHY3_TX_ARES 33 |
| #define NSS_CC_MAC4_SRDS1_CH3_XGMII_RX_ARES 34 |
| #define NSS_CC_MAC4_SRDS1_CH3_TX_ARES 35 |
| #define NSS_CC_MAC4_RX_ARES 36 |
| #define NSS_CC_MAC4_GEPHY3_RX_ARES 37 |
| #define NSS_CC_MAC4_SRDS1_CH3_XGMII_TX_ARES 38 |
| #define NSS_CC_MAC5_TX_ARES 39 |
| #define NSS_CC_MAC5_TX_SRDS0_ARES 40 |
| #define NSS_CC_MAC5_RX_ARES 41 |
| #define NSS_CC_MAC5_RX_SRDS0_ARES 42 |
| #define NSS_CC_AHB_ARES 43 |
| #define NSS_CC_SEC_CTRL_AHB_ARES 44 |
| #define NSS_CC_TLMM_ARES 45 |
| #define NSS_CC_TLMM_AHB_ARES 46 |
| #define NSS_CC_CNOC_AHB_ARES 47 |
| #define NSS_CC_MDIO_AHB_ARES 48 |
| #define NSS_CC_MDIO_MASTER_AHB_ARES 49 |
| #define NSS_CC_SRDS0_SYS_ARES 50 |
| #define NSS_CC_SRDS1_SYS_ARES 51 |
| #define NSS_CC_GEPHY0_SYS_ARES 52 |
| #define NSS_CC_GEPHY1_SYS_ARES 53 |
| #define NSS_CC_GEPHY2_SYS_ARES 54 |
| #define NSS_CC_GEPHY3_SYS_ARES 55 |
| #define NSS_CC_SEC_CTRL_ARES 56 |
| #define NSS_CC_SEC_CTRL_SENSE_ARES 57 |
| #define NSS_CC_SLEEP_ARES 58 |
| #define NSS_CC_DEBUG_ARES 59 |
| #define NSS_CC_GEPHY0_ARES 60 |
| #define NSS_CC_GEPHY1_ARES 61 |
| #define NSS_CC_GEPHY2_ARES 62 |
| #define NSS_CC_GEPHY3_ARES 63 |
| #define NSS_CC_DSP_ARES 64 |
| #define NSS_CC_GEPHY_FULL_ARES 65 |
| #define NSS_CC_GLOBAL_ARES 66 |
| #define NSS_CC_XPCS_ARES 67 |
| #endif |
