| # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) |
| %YAML 1.2 |
| --- |
| $id: http://devicetree.org/schemas/net/pcs/mediatek,sgmiisys.yaml# |
| $schema: http://devicetree.org/meta-schemas/core.yaml# |
| |
| title: MediaTek SGMIISYS Controller |
| |
| maintainers: |
| - Matthias Brugger <matthias.bgg@gmail.com> |
| |
| description: |
| The MediaTek SGMIISYS controller provides a SGMII PCS and some clocks |
| to the ethernet subsystem to which it is attached. |
| |
| properties: |
| compatible: |
| oneOf: |
| - items: |
| - enum: |
| - mediatek,mt7622-sgmiisys |
| - mediatek,mt7629-sgmiisys |
| - mediatek,mt7981-sgmiisys_0 |
| - mediatek,mt7981-sgmiisys_1 |
| - mediatek,mt7986-sgmiisys_0 |
| - mediatek,mt7986-sgmiisys_1 |
| - const: syscon |
| - items: |
| - enum: |
| - mediatek,mt7988-sgmiisys0 |
| - mediatek,mt7988-sgmiisys1 |
| - const: simple-mfd |
| - const: syscon |
| |
| reg: |
| maxItems: 1 |
| |
| '#clock-cells': |
| const: 1 |
| |
| mediatek,pnswap: |
| description: Invert polarity of the SGMII data lanes |
| type: boolean |
| |
| pcs: |
| type: object |
| description: MediaTek LynxI HSGMII PCS |
| properties: |
| compatible: |
| const: mediatek,mt7988-sgmii |
| |
| clocks: |
| maxItems: 3 |
| |
| clock-names: |
| items: |
| - const: sgmii_sel |
| - const: sgmii_tx |
| - const: sgmii_rx |
| |
| required: |
| - compatible |
| - clocks |
| - clock-names |
| |
| additionalProperties: false |
| |
| required: |
| - compatible |
| - reg |
| - '#clock-cells' |
| |
| allOf: |
| - if: |
| properties: |
| compatible: |
| contains: |
| enum: |
| - mediatek,mt7988-sgmiisys0 |
| - mediatek,mt7988-sgmiisys1 |
| |
| then: |
| required: |
| - pcs |
| |
| else: |
| properties: |
| pcs: false |
| |
| additionalProperties: false |
| |
| examples: |
| - | |
| soc { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| sgmiisys: syscon@1b128000 { |
| compatible = "mediatek,mt7622-sgmiisys", "syscon"; |
| reg = <0 0x1b128000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| }; |