Documentation/devicetree/bindings/sound/dlg,da7213.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/sound/dlg,da7213.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Dialog Semiconductor DA7212/DA7213 Audio Codec

maintainers:
  - Support Opensource <support.opensource@diasemi.com>

allOf:
  - $ref: dai-common.yaml#

properties:
  compatible:
    enum:
      - dlg,da7212
      - dlg,da7213

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-names:
    const: mclk

  "#sound-dai-cells":
    const: 0

  dlg,micbias1-lvl:
    description: Voltage (mV) for Mic Bias 1
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [ 1600, 2200, 2500, 3000 ]

  dlg,micbias2-lvl:
    description: Voltage (mV) for Mic Bias 2
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [ 1600, 2200, 2500, 3000 ]

  dlg,dmic-data-sel:
    description: DMIC channel select based on clock edge
    enum: [ lrise_rfall, lfall_rrise ]

  dlg,dmic-samplephase:
    description: When to sample audio from DMIC
    enum: [ on_clkedge, between_clkedge ]

  dlg,dmic-clkrate:
    description: DMIC clock frequency (Hz)
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [ 1500000, 3000000 ]

  VDDA-supply:
    description: Analogue power supply

  VDDIO-supply:
    description: I/O power supply

  VDDMIC-supply:
    description: Mic Bias

  VDDSP-supply:
    description: Speaker supply

  ports:
    $ref: audio-graph-port.yaml#/definitions/ports

  port:
    $ref: audio-graph-port.yaml#
    unevaluatedProperties: false

required:
  - compatible
  - reg

unevaluatedProperties: false

examples:
  - |
    i2c {
        #address-cells = <1>;
        #size-cells = <0>;

        codec@1a {
            compatible = "dlg,da7213";
            reg = <0x1a>;

            clocks = <&clks 201>;
            clock-names = "mclk";

            #sound-dai-cells = <0>;

            dlg,micbias1-lvl = <2500>;
            dlg,micbias2-lvl = <2500>;

            dlg,dmic-data-sel = "lrise_rfall";
            dlg,dmic-samplephase = "between_clkedge";
            dlg,dmic-clkrate = <3000000>;
        };
    };