| // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| /* |
| * Copyright 2021 NXP |
| */ |
| |
| /dts-v1/; |
| |
| #include "imx8ulp.dtsi" |
| |
| / { |
| model = "NXP i.MX8ULP EVK"; |
| compatible = "fsl,imx8ulp-evk", "fsl,imx8ulp"; |
| |
| chosen { |
| stdout-path = &lpuart5; |
| }; |
| |
| memory@80000000 { |
| device_type = "memory"; |
| reg = <0x0 0x80000000 0 0x80000000>; |
| }; |
| |
| reserved-memory { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| linux,cma { |
| compatible = "shared-dma-pool"; |
| reusable; |
| size = <0 0x28000000>; |
| linux,cma-default; |
| }; |
| |
| m33_reserved: noncacheable-section@a8600000 { |
| reg = <0 0xa8600000 0 0x1000000>; |
| no-map; |
| }; |
| |
| rsc_table: rsc-table@1fff8000 { |
| reg = <0 0x1fff8000 0 0x1000>; |
| no-map; |
| }; |
| |
| vdev0vring0: vdev0vring0@aff00000 { |
| reg = <0 0xaff00000 0 0x8000>; |
| no-map; |
| }; |
| |
| vdev0vring1: vdev0vring1@aff08000 { |
| reg = <0 0xaff08000 0 0x8000>; |
| no-map; |
| }; |
| |
| vdev1vring0: vdev1vring0@aff10000 { |
| reg = <0 0xaff10000 0 0x8000>; |
| no-map; |
| }; |
| |
| vdev1vring1: vdev1vring1@aff18000 { |
| reg = <0 0xaff18000 0 0x8000>; |
| no-map; |
| }; |
| |
| vdevbuffer: vdevbuffer@a8400000 { |
| compatible = "shared-dma-pool"; |
| reg = <0 0xa8400000 0 0x100000>; |
| no-map; |
| }; |
| }; |
| |
| clock_ext_rmii: clock-ext-rmii { |
| compatible = "fixed-clock"; |
| clock-frequency = <50000000>; |
| clock-output-names = "ext_rmii_clk"; |
| #clock-cells = <0>; |
| }; |
| |
| clock_ext_ts: clock-ext-ts { |
| compatible = "fixed-clock"; |
| /* External ts clock is 50MHZ from PHY on EVK board. */ |
| clock-frequency = <50000000>; |
| clock-output-names = "ext_ts_clk"; |
| #clock-cells = <0>; |
| }; |
| }; |
| |
| &cm33 { |
| mbox-names = "tx", "rx", "rxdb"; |
| mboxes = <&mu 0 1>, |
| <&mu 1 1>, |
| <&mu 3 1>; |
| memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, |
| <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>; |
| status = "okay"; |
| }; |
| |
| &flexspi2 { |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&pinctrl_flexspi2_ptd>; |
| pinctrl-1 = <&pinctrl_flexspi2_ptd>; |
| status = "okay"; |
| |
| mx25uw51345gxdi00: flash@0 { |
| compatible = "jedec,spi-nor"; |
| reg = <0>; |
| spi-max-frequency = <200000000>; |
| spi-tx-bus-width = <8>; |
| spi-rx-bus-width = <8>; |
| }; |
| }; |
| |
| &lpuart5 { |
| /* console */ |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&pinctrl_lpuart5>; |
| pinctrl-1 = <&pinctrl_lpuart5>; |
| status = "okay"; |
| }; |
| |
| &lpi2c7 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clock-frequency = <400000>; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&pinctrl_lpi2c7>; |
| pinctrl-1 = <&pinctrl_lpi2c7>; |
| status = "okay"; |
| |
| ptn5150_1: typec@1d { |
| compatible = "nxp,ptn5150"; |
| reg = <0x1d>; |
| int-gpios = <&gpiof 3 IRQ_TYPE_EDGE_FALLING>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_typec1>; |
| status = "disabled"; |
| }; |
| |
| pcal6408: gpio@21 { |
| compatible = "nxp,pcal9554b"; |
| reg = <0x21>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| }; |
| |
| ptn5150_2: typec@3d { |
| compatible = "nxp,ptn5150"; |
| reg = <0x3d>; |
| int-gpios = <&gpiof 5 IRQ_TYPE_EDGE_FALLING>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_typec2>; |
| status = "disabled"; |
| }; |
| }; |
| |
| &usbotg1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_usb1>; |
| dr_mode = "otg"; |
| hnp-disable; |
| srp-disable; |
| adp-disable; |
| over-current-active-low; |
| status = "okay"; |
| }; |
| |
| &usbphy1 { |
| fsl,tx-d-cal = <110>; |
| status = "okay"; |
| }; |
| |
| &usbmisc1 { |
| status = "okay"; |
| }; |
| |
| &usbotg2 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_usb2>; |
| dr_mode = "otg"; |
| hnp-disable; |
| srp-disable; |
| adp-disable; |
| over-current-active-low; |
| status = "okay"; |
| }; |
| |
| &usbphy2 { |
| fsl,tx-d-cal = <110>; |
| status = "okay"; |
| }; |
| |
| &usbmisc2 { |
| status = "okay"; |
| }; |
| |
| &usdhc0 { |
| pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; |
| pinctrl-0 = <&pinctrl_usdhc0>; |
| pinctrl-1 = <&pinctrl_usdhc0>; |
| pinctrl-2 = <&pinctrl_usdhc0>; |
| pinctrl-3 = <&pinctrl_usdhc0>; |
| non-removable; |
| bus-width = <8>; |
| status = "okay"; |
| }; |
| |
| &fec { |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&pinctrl_enet>; |
| pinctrl-1 = <&pinctrl_enet>; |
| clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>, |
| <&pcc4 IMX8ULP_CLK_ENET>, |
| <&cgc1 IMX8ULP_CLK_ENET_TS_SEL>, |
| <&clock_ext_rmii>; |
| clock-names = "ipg", "ahb", "ptp", "enet_clk_ref"; |
| assigned-clocks = <&cgc1 IMX8ULP_CLK_ENET_TS_SEL>; |
| assigned-clock-parents = <&clock_ext_ts>; |
| phy-mode = "rmii"; |
| phy-handle = <ðphy>; |
| status = "okay"; |
| |
| mdio { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| ethphy: ethernet-phy@1 { |
| reg = <1>; |
| micrel,led-mode = <1>; |
| }; |
| }; |
| }; |
| |
| &mu { |
| status = "okay"; |
| }; |
| |
| &iomuxc1 { |
| pinctrl_enet: enetgrp { |
| fsl,pins = < |
| MX8ULP_PAD_PTE15__ENET0_MDC 0x43 |
| MX8ULP_PAD_PTE14__ENET0_MDIO 0x43 |
| MX8ULP_PAD_PTE17__ENET0_RXER 0x43 |
| MX8ULP_PAD_PTE18__ENET0_CRS_DV 0x43 |
| MX8ULP_PAD_PTF1__ENET0_RXD0 0x43 |
| MX8ULP_PAD_PTE20__ENET0_RXD1 0x43 |
| MX8ULP_PAD_PTE16__ENET0_TXEN 0x43 |
| MX8ULP_PAD_PTE23__ENET0_TXD0 0x43 |
| MX8ULP_PAD_PTE22__ENET0_TXD1 0x43 |
| MX8ULP_PAD_PTE19__ENET0_REFCLK 0x43 |
| MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x43 |
| >; |
| }; |
| |
| pinctrl_flexspi2_ptd: flexspi2ptdgrp { |
| fsl,pins = < |
| |
| MX8ULP_PAD_PTD12__FLEXSPI2_A_SS0_B 0x42 |
| MX8ULP_PAD_PTD13__FLEXSPI2_A_SCLK 0x42 |
| MX8ULP_PAD_PTD14__FLEXSPI2_A_DATA3 0x42 |
| MX8ULP_PAD_PTD15__FLEXSPI2_A_DATA2 0x42 |
| MX8ULP_PAD_PTD16__FLEXSPI2_A_DATA1 0x42 |
| MX8ULP_PAD_PTD17__FLEXSPI2_A_DATA0 0x42 |
| MX8ULP_PAD_PTD18__FLEXSPI2_A_DQS 0x42 |
| MX8ULP_PAD_PTD19__FLEXSPI2_A_DATA7 0x42 |
| MX8ULP_PAD_PTD20__FLEXSPI2_A_DATA6 0x42 |
| MX8ULP_PAD_PTD21__FLEXSPI2_A_DATA5 0x42 |
| MX8ULP_PAD_PTD22__FLEXSPI2_A_DATA4 0x42 |
| >; |
| }; |
| |
| pinctrl_lpuart5: lpuart5grp { |
| fsl,pins = < |
| MX8ULP_PAD_PTF14__LPUART5_TX 0x3 |
| MX8ULP_PAD_PTF15__LPUART5_RX 0x3 |
| >; |
| }; |
| |
| pinctrl_lpi2c7: lpi2c7grp { |
| fsl,pins = < |
| MX8ULP_PAD_PTE12__LPI2C7_SCL 0x20 |
| MX8ULP_PAD_PTE13__LPI2C7_SDA 0x20 |
| >; |
| }; |
| |
| pinctrl_typec1: typec1grp { |
| fsl,pins = < |
| MX8ULP_PAD_PTF3__PTF3 0x3 |
| >; |
| }; |
| |
| pinctrl_typec2: typec2grp { |
| fsl,pins = < |
| MX8ULP_PAD_PTF5__PTF5 0x3 |
| >; |
| }; |
| |
| pinctrl_usb1: usb1grp { |
| fsl,pins = < |
| MX8ULP_PAD_PTF2__USB0_ID 0x10003 |
| MX8ULP_PAD_PTF4__USB0_OC 0x10003 |
| >; |
| }; |
| |
| pinctrl_usb2: usb2grp { |
| fsl,pins = < |
| MX8ULP_PAD_PTD23__USB1_ID 0x10003 |
| MX8ULP_PAD_PTF6__USB1_OC 0x10003 |
| >; |
| }; |
| |
| pinctrl_usdhc0: usdhc0grp { |
| fsl,pins = < |
| MX8ULP_PAD_PTD1__SDHC0_CMD 0x3 |
| MX8ULP_PAD_PTD2__SDHC0_CLK 0x10002 |
| MX8ULP_PAD_PTD10__SDHC0_D0 0x3 |
| MX8ULP_PAD_PTD9__SDHC0_D1 0x3 |
| MX8ULP_PAD_PTD8__SDHC0_D2 0x3 |
| MX8ULP_PAD_PTD7__SDHC0_D3 0x3 |
| MX8ULP_PAD_PTD6__SDHC0_D4 0x3 |
| MX8ULP_PAD_PTD5__SDHC0_D5 0x3 |
| MX8ULP_PAD_PTD4__SDHC0_D6 0x3 |
| MX8ULP_PAD_PTD3__SDHC0_D7 0x3 |
| MX8ULP_PAD_PTD11__SDHC0_DQS 0x10002 |
| >; |
| }; |
| }; |
