| # SPDX-License-Identifier: GPL-2.0-only |
| # |
| # FPGA framework configuration |
| # |
| |
| menuconfig FPGA |
| tristate "FPGA Configuration Framework" |
| help |
| Say Y here if you want support for configuring FPGAs from the |
| kernel. The FPGA framework adds a FPGA manager class and FPGA |
| manager drivers. |
| |
| if FPGA |
| |
| config FPGA_MGR_SOCFPGA |
| tristate "Altera SOCFPGA FPGA Manager" |
| depends on ARCH_SOCFPGA || COMPILE_TEST |
| help |
| FPGA manager driver support for Altera SOCFPGA. |
| |
| config FPGA_MGR_SOCFPGA_A10 |
| tristate "Altera SoCFPGA Arria10" |
| depends on ARCH_SOCFPGA || COMPILE_TEST |
| select REGMAP_MMIO |
| help |
| FPGA manager driver support for Altera Arria10 SoCFPGA. |
| |
| config ALTERA_PR_IP_CORE |
| tristate "Altera Partial Reconfiguration IP Core" |
| help |
| Core driver support for Altera Partial Reconfiguration IP component |
| |
| config ALTERA_PR_IP_CORE_PLAT |
| tristate "Platform support of Altera Partial Reconfiguration IP Core" |
| depends on ALTERA_PR_IP_CORE && OF && HAS_IOMEM |
| help |
| Platform driver support for Altera Partial Reconfiguration IP |
| component |
| |
| config FPGA_MGR_ALTERA_PS_SPI |
| tristate "Altera FPGA Passive Serial over SPI" |
| depends on SPI |
| select BITREVERSE |
| help |
| FPGA manager driver support for Altera Arria/Cyclone/Stratix |
| using the passive serial interface over SPI. |
| |
| config FPGA_MGR_ALTERA_CVP |
| tristate "Altera CvP FPGA Manager" |
| depends on PCI |
| help |
| FPGA manager driver support for Arria-V, Cyclone-V, Stratix-V, |
| Arria 10 and Stratix10 Altera FPGAs using the CvP interface over PCIe. |
| |
| config FPGA_MGR_ZYNQ_FPGA |
| tristate "Xilinx Zynq FPGA" |
| depends on ARCH_ZYNQ || COMPILE_TEST |
| help |
| FPGA manager driver support for Xilinx Zynq FPGAs. |
| |
| config FPGA_MGR_STRATIX10_SOC |
| tristate "Intel Stratix10 SoC FPGA Manager" |
| depends on (ARCH_STRATIX10 && INTEL_STRATIX10_SERVICE) |
| help |
| FPGA manager driver support for the Intel Stratix10 SoC. |
| |
| config FPGA_MGR_XILINX_SPI |
| tristate "Xilinx Configuration over Slave Serial (SPI)" |
| depends on SPI |
| help |
| FPGA manager driver support for Xilinx FPGA configuration |
| over slave serial interface. |
| |
| config FPGA_MGR_ICE40_SPI |
| tristate "Lattice iCE40 SPI" |
| depends on OF && SPI |
| help |
| FPGA manager driver support for Lattice iCE40 FPGAs over SPI. |
| |
| config FPGA_MGR_MACHXO2_SPI |
| tristate "Lattice MachXO2 SPI" |
| depends on SPI |
| help |
| FPGA manager driver support for Lattice MachXO2 configuration |
| over slave SPI interface. |
| |
| config FPGA_MGR_TS73XX |
| tristate "Technologic Systems TS-73xx SBC FPGA Manager" |
| depends on ARCH_EP93XX && MACH_TS72XX |
| help |
| FPGA manager driver support for the Altera Cyclone II FPGA |
| present on the TS-73xx SBC boards. |
| |
| config FPGA_BRIDGE |
| tristate "FPGA Bridge Framework" |
| help |
| Say Y here if you want to support bridges connected between host |
| processors and FPGAs or between FPGAs. |
| |
| config SOCFPGA_FPGA_BRIDGE |
| tristate "Altera SoCFPGA FPGA Bridges" |
| depends on ARCH_SOCFPGA && FPGA_BRIDGE |
| help |
| Say Y to enable drivers for FPGA bridges for Altera SOCFPGA |
| devices. |
| |
| config ALTERA_FREEZE_BRIDGE |
| tristate "Altera FPGA Freeze Bridge" |
| depends on FPGA_BRIDGE && HAS_IOMEM |
| help |
| Say Y to enable drivers for Altera FPGA Freeze bridges. A |
| freeze bridge is a bridge that exists in the FPGA fabric to |
| isolate one region of the FPGA from the busses while that |
| region is being reprogrammed. |
| |
| config XILINX_PR_DECOUPLER |
| tristate "Xilinx LogiCORE PR Decoupler" |
| depends on FPGA_BRIDGE |
| depends on HAS_IOMEM |
| help |
| Say Y to enable drivers for Xilinx LogiCORE PR Decoupler. |
| The PR Decoupler exists in the FPGA fabric to isolate one |
| region of the FPGA from the busses while that region is |
| being reprogrammed during partial reconfig. |
| |
| config FPGA_REGION |
| tristate "FPGA Region" |
| depends on FPGA_BRIDGE |
| help |
| FPGA Region common code. A FPGA Region controls a FPGA Manager |
| and the FPGA Bridges associated with either a reconfigurable |
| region of an FPGA or a whole FPGA. |
| |
| config OF_FPGA_REGION |
| tristate "FPGA Region Device Tree Overlay Support" |
| depends on OF && FPGA_REGION |
| help |
| Support for loading FPGA images by applying a Device Tree |
| overlay. |
| |
| config FPGA_DFL |
| tristate "FPGA Device Feature List (DFL) support" |
| select FPGA_BRIDGE |
| select FPGA_REGION |
| depends on HAS_IOMEM |
| help |
| Device Feature List (DFL) defines a feature list structure that |
| creates a linked list of feature headers within the MMIO space |
| to provide an extensible way of adding features for FPGA. |
| Driver can walk through the feature headers to enumerate feature |
| devices (e.g. FPGA Management Engine, Port and Accelerator |
| Function Unit) and their private features for target FPGA devices. |
| |
| Select this option to enable common support for Field-Programmable |
| Gate Array (FPGA) solutions which implement Device Feature List. |
| It provides enumeration APIs and feature device infrastructure. |
| |
| config FPGA_DFL_FME |
| tristate "FPGA DFL FME Driver" |
| depends on FPGA_DFL && HWMON && PERF_EVENTS |
| help |
| The FPGA Management Engine (FME) is a feature device implemented |
| under Device Feature List (DFL) framework. Select this option to |
| enable the platform device driver for FME which implements all |
| FPGA platform level management features. There shall be one FME |
| per DFL based FPGA device. |
| |
| config FPGA_DFL_FME_MGR |
| tristate "FPGA DFL FME Manager Driver" |
| depends on FPGA_DFL_FME && HAS_IOMEM |
| help |
| Say Y to enable FPGA Manager driver for FPGA Management Engine. |
| |
| config FPGA_DFL_FME_BRIDGE |
| tristate "FPGA DFL FME Bridge Driver" |
| depends on FPGA_DFL_FME && HAS_IOMEM |
| help |
| Say Y to enable FPGA Bridge driver for FPGA Management Engine. |
| |
| config FPGA_DFL_FME_REGION |
| tristate "FPGA DFL FME Region Driver" |
| depends on FPGA_DFL_FME && HAS_IOMEM |
| help |
| Say Y to enable FPGA Region driver for FPGA Management Engine. |
| |
| config FPGA_DFL_AFU |
| tristate "FPGA DFL AFU Driver" |
| depends on FPGA_DFL |
| help |
| This is the driver for FPGA Accelerated Function Unit (AFU) which |
| implements AFU and Port management features. A User AFU connects |
| to the FPGA infrastructure via a Port. There may be more than one |
| Port/AFU per DFL based FPGA device. |
| |
| config FPGA_DFL_NIOS_INTEL_PAC_N3000 |
| tristate "FPGA DFL NIOS Driver for Intel PAC N3000" |
| depends on FPGA_DFL |
| select REGMAP |
| help |
| This is the driver for the N3000 Nios private feature on Intel |
| PAC (Programmable Acceleration Card) N3000. It communicates |
| with the embedded Nios processor to configure the retimers on |
| the card. It also instantiates the SPI master (spi-altera) for |
| the card's BMC (Board Management Controller). |
| |
| config FPGA_DFL_PCI |
| tristate "FPGA DFL PCIe Device Driver" |
| depends on PCI && FPGA_DFL |
| help |
| Select this option to enable PCIe driver for PCIe-based |
| Field-Programmable Gate Array (FPGA) solutions which implement |
| the Device Feature List (DFL). This driver provides interfaces |
| for userspace applications to configure, enumerate, open and access |
| FPGA accelerators on the FPGA DFL devices, enables system level |
| management functions such as FPGA partial reconfiguration, power |
| management and virtualization with DFL framework and DFL feature |
| device drivers. |
| |
| To compile this as a module, choose M here. |
| |
| config FPGA_MGR_ZYNQMP_FPGA |
| tristate "Xilinx ZynqMP FPGA" |
| depends on ZYNQMP_FIRMWARE || (!ZYNQMP_FIRMWARE && COMPILE_TEST) |
| help |
| FPGA manager driver support for Xilinx ZynqMP FPGAs. |
| This driver uses the processor configuration port(PCAP) |
| to configure the programmable logic(PL) through PS |
| on ZynqMP SoC. |
| |
| endif # FPGA |