| # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| %YAML 1.2 |
| --- |
| $id: http://devicetree.org/schemas/iio/resolver/adi,ad2s1210.yaml# |
| $schema: http://devicetree.org/meta-schemas/core.yaml# |
| |
| title: Analog Devices AD2S1210 Resolver-to-Digital Converter |
| |
| maintainers: |
| - Michael Hennerich <michael.hennerich@analog.com> |
| |
| description: | |
| The AD2S1210 is a complete 10-bit to 16-bit resolution tracking |
| resolver-to-digital converter, integrating an on-board programmable |
| sinusoidal oscillator that provides sine wave excitation for |
| resolvers. |
| |
| The AD2S1210 allows the user to read the angular position or the |
| angular velocity data directly from the parallel outputs or through |
| the serial interface. |
| |
| The mode of operation of the communication channel (parallel or serial) is |
| selected by the A0 and A1 input pins. In normal mode, data is latched by |
| toggling the SAMPLE line and can then be read directly. In configuration mode, |
| data is read or written using a register access scheme (address byte with |
| read/write flag and data byte). |
| |
| A1 A0 Result |
| 0 0 Normal mode - position output |
| 0 1 Normal mode - velocity output |
| 1 0 Reserved |
| 1 1 Configuration mode |
| |
| In normal mode, the resolution of the digital output is selected using |
| the RES0 and RES1 input pins. In configuration mode, the resolution is |
| selected by setting the RES0 and RES1 bits in the control register. |
| |
| RES1 RES0 Resolution (Bits) |
| 0 0 10 |
| 0 1 12 |
| 1 0 14 |
| 1 1 16 |
| |
| Note on SPI connections: The CS line on the AD2S1210 should hard-wired to |
| logic low and the WR/FSYNC line on the AD2S1210 should be connected to the |
| SPI CSn output of the SPI controller. |
| |
| Datasheet: |
| https://www.analog.com/media/en/technical-documentation/data-sheets/ad2s1210.pdf |
| |
| properties: |
| compatible: |
| const: adi,ad2s1210 |
| |
| reg: |
| maxItems: 1 |
| |
| spi-max-frequency: |
| maximum: 25000000 |
| |
| spi-cpha: true |
| |
| avdd-supply: |
| description: |
| A 4.75 to 5.25 V regulator that powers the Analog Supply Voltage (AVDD) |
| pin. |
| |
| dvdd-supply: |
| description: |
| A 4.75 to 5.25 V regulator that powers the Digital Supply Voltage (DVDD) |
| pin. |
| |
| vdrive-supply: |
| description: |
| A 2.3 to 5.25 V regulator that powers the Logic Power Supply Input |
| (VDrive) pin. |
| |
| clocks: |
| maxItems: 1 |
| description: External oscillator clock (CLKIN). |
| |
| reset-gpios: |
| description: |
| GPIO connected to the /RESET pin. As the line needs to be low for the |
| reset to be active, it should be configured as GPIO_ACTIVE_LOW. |
| maxItems: 1 |
| |
| sample-gpios: |
| description: |
| GPIO connected to the /SAMPLE pin. As the line needs to be low to trigger |
| a sample, it should be configured as GPIO_ACTIVE_LOW. |
| maxItems: 1 |
| |
| mode-gpios: |
| description: |
| GPIO lines connected to the A0 and A1 pins. These pins select the data |
| transfer mode. |
| minItems: 2 |
| maxItems: 2 |
| |
| resolution-gpios: |
| description: |
| GPIO lines connected to the RES0 and RES1 pins. These pins select the |
| resolution of the digital output. If omitted, it is assumed that the |
| RES0 and RES1 pins are hard-wired to match the assigned-resolution-bits |
| property. |
| minItems: 2 |
| maxItems: 2 |
| |
| fault-gpios: |
| description: |
| GPIO lines connected to the LOT and DOS pins. These pins combined indicate |
| the type of fault present, if any. As these pins a pulled low to indicate |
| a fault condition, they should be configured as GPIO_ACTIVE_LOW. |
| minItems: 2 |
| maxItems: 2 |
| |
| adi,fixed-mode: |
| description: |
| This is used to indicate the selected mode if A0 and A1 are hard-wired |
| instead of connected to GPIOS (i.e. mode-gpios is omitted). |
| $ref: /schemas/types.yaml#/definitions/string |
| enum: [config, velocity, position] |
| |
| assigned-resolution-bits: |
| description: |
| Resolution of the digital output required by the application. This |
| determines the precision of the angle and/or the maximum speed that can |
| be measured. If resolution-gpios is omitted, it is assumed that RES0 and |
| RES1 are hard-wired to match this value. |
| enum: [10, 12, 14, 16] |
| |
| required: |
| - compatible |
| - reg |
| - spi-cpha |
| - avdd-supply |
| - dvdd-supply |
| - vdrive-supply |
| - clocks |
| - sample-gpios |
| - assigned-resolution-bits |
| |
| oneOf: |
| - required: |
| - mode-gpios |
| - required: |
| - adi,fixed-mode |
| |
| allOf: |
| - $ref: /schemas/spi/spi-peripheral-props.yaml# |
| |
| unevaluatedProperties: false |
| |
| examples: |
| - | |
| #include <dt-bindings/gpio/gpio.h> |
| |
| spi { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| resolver@0 { |
| compatible = "adi,ad2s1210"; |
| reg = <0>; |
| spi-max-frequency = <20000000>; |
| spi-cpha; |
| avdd-supply = <&avdd_regulator>; |
| dvdd-supply = <&dvdd_regulator>; |
| vdrive-supply = <&vdrive_regulator>; |
| clocks = <&ext_osc>; |
| sample-gpios = <&gpio0 90 GPIO_ACTIVE_LOW>; |
| mode-gpios = <&gpio0 86 0>, <&gpio0 87 0>; |
| resolution-gpios = <&gpio0 88 0>, <&gpio0 89 0>; |
| assigned-resolution-bits = <16>; |
| }; |
| }; |