| // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) |
| /* |
| * Copyright (C) STMicroelectronics 2021 - All Rights Reserved |
| * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> |
| */ |
| #include <dt-bindings/pinctrl/stm32-pinfunc.h> |
| |
| &pinctrl { |
| /omit-if-no-ref/ |
| adc1_pins_a: adc1-pins-0 { |
| pins { |
| pinmux = <STM32_PINMUX('A', 3, ANALOG)>; /* ADC1 in12 */ |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| adc1_usb_cc_pins_a: adc1-usb-cc-pins-0 { |
| pins { |
| pinmux = <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */ |
| <STM32_PINMUX('A', 3, ANALOG)>; /* ADC1 in12 */ |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| adc1_usb_cc_pins_b: adc1-usb-cc-pins-1 { |
| pins { |
| pinmux = <STM32_PINMUX('A', 5, ANALOG)>, /* ADC1_INP2 */ |
| <STM32_PINMUX('F', 13, ANALOG)>; /* ADC1_INP11 */ |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| dcmipp_pins_a: dcmi-0 { |
| pins1 { |
| pinmux = <STM32_PINMUX('H', 8, AF13)>,/* DCMI_HSYNC */ |
| <STM32_PINMUX('G', 9, AF13)>,/* DCMI_VSYNC */ |
| <STM32_PINMUX('B', 7, AF14)>,/* DCMI_PIXCLK */ |
| <STM32_PINMUX('A', 9, AF13)>,/* DCMI_D0 */ |
| <STM32_PINMUX('D', 0, AF13)>,/* DCMI_D1 */ |
| <STM32_PINMUX('G', 10, AF13)>,/* DCMI_D2 */ |
| <STM32_PINMUX('E', 4, AF13)>,/* DCMI_D3 */ |
| <STM32_PINMUX('D', 11, AF14)>,/* DCMI_D4 */ |
| <STM32_PINMUX('D', 3, AF13)>,/* DCMI_D5 */ |
| <STM32_PINMUX('B', 8, AF13)>,/* DCMI_D6 */ |
| <STM32_PINMUX('E', 14, AF13)>;/* DCMI_D7 */ |
| bias-disable; |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| dcmipp_sleep_pins_a: dcmi-sleep-0 { |
| pins1 { |
| pinmux = <STM32_PINMUX('H', 8, ANALOG)>,/* DCMI_HSYNC */ |
| <STM32_PINMUX('G', 9, ANALOG)>,/* DCMI_VSYNC */ |
| <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_PIXCLK */ |
| <STM32_PINMUX('A', 9, ANALOG)>,/* DCMI_D0 */ |
| <STM32_PINMUX('D', 0, ANALOG)>,/* DCMI_D1 */ |
| <STM32_PINMUX('G', 10, ANALOG)>,/* DCMI_D2 */ |
| <STM32_PINMUX('E', 4, ANALOG)>,/* DCMI_D3 */ |
| <STM32_PINMUX('D', 11, ANALOG)>,/* DCMI_D4 */ |
| <STM32_PINMUX('D', 3, ANALOG)>,/* DCMI_D5 */ |
| <STM32_PINMUX('B', 8, ANALOG)>,/* DCMI_D6 */ |
| <STM32_PINMUX('E', 14, ANALOG)>;/* DCMI_D7 */ |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| eth1_rgmii_pins_a: eth1-rgmii-0 { |
| pins1 { |
| pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */ |
| <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */ |
| <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */ |
| <STM32_PINMUX('E', 5, AF10)>, /* ETH_RGMII_TXD3 */ |
| <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */ |
| <STM32_PINMUX('C', 1, AF11)>, /* ETH_RGMII_GTX_CLK */ |
| <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */ |
| <STM32_PINMUX('G', 2, AF11)>; /* ETH_MDC */ |
| bias-disable; |
| drive-push-pull; |
| slew-rate = <2>; |
| }; |
| |
| pins2 { |
| pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */ |
| <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */ |
| <STM32_PINMUX('B', 0, AF11)>, /* ETH_RGMII_RXD2 */ |
| <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */ |
| <STM32_PINMUX('A', 7, AF11)>, /* ETH_RGMII_RX_CTL */ |
| <STM32_PINMUX('D', 7, AF10)>; /* ETH_RGMII_RX_CLK */ |
| bias-disable; |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| eth1_rgmii_sleep_pins_a: eth1-rgmii-sleep-0 { |
| pins1 { |
| pinmux = <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */ |
| <STM32_PINMUX('G', 2, AF11)>; /* ETH_MDC */ |
| bias-disable; |
| drive-push-pull; |
| slew-rate = <2>; |
| }; |
| |
| pins2 { |
| pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */ |
| <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */ |
| <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */ |
| <STM32_PINMUX('E', 5, ANALOG)>, /* ETH_RGMII_TXD3 */ |
| <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */ |
| <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_RGMII_GTX_CLK */ |
| <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */ |
| <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */ |
| <STM32_PINMUX('B', 0, ANALOG)>, /* ETH_RGMII_RXD1 */ |
| <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD1 */ |
| <STM32_PINMUX('A', 7, ANALOG)>, /* ETH_RGMII_RX_CTL */ |
| <STM32_PINMUX('D', 7, ANALOG)>; /* ETH_RGMII_RX_CLK */ |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| eth1_rmii_pins_a: eth1-rmii-0 { |
| pins1 { |
| pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH_RMII_TXD0 */ |
| <STM32_PINMUX('G', 14, AF11)>, /* ETH_RMII_TXD1 */ |
| <STM32_PINMUX('B', 11, AF11)>, /* ETH_RMII_TX_EN */ |
| <STM32_PINMUX('A', 1, AF11)>, /* ETH_RMII_REF_CLK */ |
| <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */ |
| <STM32_PINMUX('G', 2, AF11)>; /* ETH_MDC */ |
| bias-disable; |
| drive-push-pull; |
| slew-rate = <1>; |
| }; |
| |
| pins2 { |
| pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RMII_RXD0 */ |
| <STM32_PINMUX('C', 5, AF11)>, /* ETH_RMII_RXD1 */ |
| <STM32_PINMUX('C', 1, AF10)>; /* ETH_RMII_CRS_DV */ |
| bias-disable; |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| eth1_rmii_sleep_pins_a: eth1-rmii-sleep-0 { |
| pins1 { |
| pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RMII_TXD0 */ |
| <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RMII_TXD1 */ |
| <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RMII_TX_EN */ |
| <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RMII_REF_CLK */ |
| <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */ |
| <STM32_PINMUX('G', 2, ANALOG)>, /* ETH_MDC */ |
| <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RMII_RXD0 */ |
| <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RMII_RXD1 */ |
| <STM32_PINMUX('C', 1, ANALOG)>; /* ETH_RMII_CRS_DV */ |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| eth2_rgmii_pins_a: eth2-rgmii-0 { |
| pins1 { |
| pinmux = <STM32_PINMUX('F', 7, AF11)>, /* ETH_RGMII_TXD0 */ |
| <STM32_PINMUX('G', 11, AF10)>, /* ETH_RGMII_TXD1 */ |
| <STM32_PINMUX('G', 1, AF10)>, /* ETH_RGMII_TXD2 */ |
| <STM32_PINMUX('E', 6, AF11)>, /* ETH_RGMII_TXD3 */ |
| <STM32_PINMUX('F', 6, AF11)>, /* ETH_RGMII_TX_CTL */ |
| <STM32_PINMUX('G', 3, AF10)>, /* ETH_RGMII_GTX_CLK */ |
| <STM32_PINMUX('B', 6, AF11)>, /* ETH_MDIO */ |
| <STM32_PINMUX('G', 5, AF10)>; /* ETH_MDC */ |
| bias-disable; |
| drive-push-pull; |
| slew-rate = <2>; |
| }; |
| |
| pins2 { |
| pinmux = <STM32_PINMUX('F', 4, AF11)>, /* ETH_RGMII_RXD0 */ |
| <STM32_PINMUX('E', 2, AF10)>, /* ETH_RGMII_RXD1 */ |
| <STM32_PINMUX('H', 6, AF12)>, /* ETH_RGMII_RXD2 */ |
| <STM32_PINMUX('A', 8, AF11)>, /* ETH_RGMII_RXD3 */ |
| <STM32_PINMUX('A', 12, AF11)>, /* ETH_RGMII_RX_CTL */ |
| <STM32_PINMUX('H', 11, AF11)>; /* ETH_RGMII_RX_CLK */ |
| bias-disable; |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| eth2_rgmii_sleep_pins_a: eth2-rgmii-sleep-0 { |
| pins1 { |
| pinmux = <STM32_PINMUX('B', 6, AF11)>, /* ETH_MDIO */ |
| <STM32_PINMUX('G', 5, AF10)>; /* ETH_MDC */ |
| bias-disable; |
| drive-push-pull; |
| slew-rate = <2>; |
| }; |
| |
| pins2 { |
| pinmux = <STM32_PINMUX('F', 7, ANALOG)>, /* ETH_RGMII_TXD0 */ |
| <STM32_PINMUX('G', 11, ANALOG)>, /* ETH_RGMII_TXD1 */ |
| <STM32_PINMUX('G', 1, ANALOG)>, /* ETH_RGMII_TXD2 */ |
| <STM32_PINMUX('E', 6, ANALOG)>, /* ETH_RGMII_TXD3 */ |
| <STM32_PINMUX('F', 6, ANALOG)>, /* ETH_RGMII_TX_CTL */ |
| <STM32_PINMUX('G', 3, ANALOG)>, /* ETH_RGMII_GTX_CLK */ |
| <STM32_PINMUX('F', 4, ANALOG)>, /* ETH_RGMII_RXD0 */ |
| <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_RXD1 */ |
| <STM32_PINMUX('H', 6, ANALOG)>, /* ETH_RGMII_RXD2 */ |
| <STM32_PINMUX('A', 8, ANALOG)>, /* ETH_RGMII_RXD3 */ |
| <STM32_PINMUX('A', 12, ANALOG)>, /* ETH_RGMII_RX_CTL */ |
| <STM32_PINMUX('H', 11, ANALOG)>; /* ETH_RGMII_RX_CLK */ |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| eth2_rmii_pins_a: eth2-rmii-0 { |
| pins1 { |
| pinmux = <STM32_PINMUX('F', 7, AF11)>, /* ETH_RMII_TXD0 */ |
| <STM32_PINMUX('G', 11, AF10)>, /* ETH_RMII_TXD1 */ |
| <STM32_PINMUX('G', 8, AF13)>, /* ETH_RMII_ETHCK */ |
| <STM32_PINMUX('F', 6, AF11)>, /* ETH_RMII_TX_EN */ |
| <STM32_PINMUX('B', 2, AF11)>, /* ETH_MDIO */ |
| <STM32_PINMUX('G', 5, AF10)>; /* ETH_MDC */ |
| bias-disable; |
| drive-push-pull; |
| slew-rate = <1>; |
| }; |
| |
| pins2 { |
| pinmux = <STM32_PINMUX('F', 4, AF11)>, /* ETH_RMII_RXD0 */ |
| <STM32_PINMUX('E', 2, AF10)>, /* ETH_RMII_RXD1 */ |
| <STM32_PINMUX('A', 12, AF11)>; /* ETH_RMII_CRS_DV */ |
| bias-disable; |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| eth2_rmii_sleep_pins_a: eth2-rmii-sleep-0 { |
| pins1 { |
| pinmux = <STM32_PINMUX('F', 7, ANALOG)>, /* ETH_RMII_TXD0 */ |
| <STM32_PINMUX('G', 11, ANALOG)>, /* ETH_RMII_TXD1 */ |
| <STM32_PINMUX('G', 8, ANALOG)>, /* ETH_RMII_ETHCK */ |
| <STM32_PINMUX('F', 6, ANALOG)>, /* ETH_RMII_TX_EN */ |
| <STM32_PINMUX('B', 2, ANALOG)>, /* ETH_MDIO */ |
| <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_MDC */ |
| <STM32_PINMUX('F', 4, ANALOG)>, /* ETH_RMII_RXD0 */ |
| <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RMII_RXD1 */ |
| <STM32_PINMUX('A', 12, ANALOG)>; /* ETH_RMII_CRS_DV */ |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| goodix_pins_a: goodix-0 { |
| /* |
| * touchscreen reset needs to be configured |
| * via the pinctrl not the driver (a pull-down resistor |
| * has been soldered onto the reset line which forces |
| * the touchscreen to reset state). |
| */ |
| pins1 { |
| pinmux = <STM32_PINMUX('H', 2, GPIO)>; |
| output-high; |
| bias-pull-up; |
| }; |
| /* |
| * Interrupt line must have a pull-down resistor |
| * in order to freeze the i2c address at 0x5D |
| */ |
| pins2 { |
| pinmux = <STM32_PINMUX('F', 5, GPIO)>; |
| bias-pull-down; |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| i2c1_pins_a: i2c1-0 { |
| pins { |
| pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */ |
| <STM32_PINMUX('E', 8, AF5)>; /* I2C1_SDA */ |
| bias-disable; |
| drive-open-drain; |
| slew-rate = <0>; |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| i2c1_sleep_pins_a: i2c1-sleep-0 { |
| pins { |
| pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */ |
| <STM32_PINMUX('E', 8, ANALOG)>; /* I2C1_SDA */ |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| i2c5_pins_a: i2c5-0 { |
| pins { |
| pinmux = <STM32_PINMUX('D', 1, AF4)>, /* I2C5_SCL */ |
| <STM32_PINMUX('H', 6, AF4)>; /* I2C5_SDA */ |
| bias-disable; |
| drive-open-drain; |
| slew-rate = <0>; |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| i2c5_sleep_pins_a: i2c5-sleep-0 { |
| pins { |
| pinmux = <STM32_PINMUX('D', 1, ANALOG)>, /* I2C5_SCL */ |
| <STM32_PINMUX('H', 6, ANALOG)>; /* I2C5_SDA */ |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| i2c5_pins_b: i2c5-1 { |
| pins { |
| pinmux = <STM32_PINMUX('D', 1, AF4)>, /* I2C5_SCL */ |
| <STM32_PINMUX('E', 13, AF4)>; /* I2C5_SDA */ |
| bias-disable; |
| drive-open-drain; |
| slew-rate = <0>; |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| i2c5_sleep_pins_b: i2c5-sleep-1 { |
| pins { |
| pinmux = <STM32_PINMUX('D', 1, ANALOG)>, /* I2C5_SCL */ |
| <STM32_PINMUX('E', 13, ANALOG)>; /* I2C5_SDA */ |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| ltdc_pins_a: ltdc-0 { |
| pins { |
| pinmux = <STM32_PINMUX('D', 9, AF13)>, /* LCD_CLK */ |
| <STM32_PINMUX('C', 6, AF14)>, /* LCD_HSYNC */ |
| <STM32_PINMUX('G', 4, AF11)>, /* LCD_VSYNC */ |
| <STM32_PINMUX('H', 9, AF11)>, /* LCD_DE */ |
| <STM32_PINMUX('G', 7, AF14)>, /* LCD_R2 */ |
| <STM32_PINMUX('B', 12, AF13)>, /* LCD_R3 */ |
| <STM32_PINMUX('D', 14, AF14)>, /* LCD_R4 */ |
| <STM32_PINMUX('E', 7, AF14)>, /* LCD_R5 */ |
| <STM32_PINMUX('E', 13, AF14)>, /* LCD_R6 */ |
| <STM32_PINMUX('E', 9, AF14)>, /* LCD_R7 */ |
| <STM32_PINMUX('H', 13, AF14)>, /* LCD_G2 */ |
| <STM32_PINMUX('F', 3, AF14)>, /* LCD_G3 */ |
| <STM32_PINMUX('D', 5, AF14)>, /* LCD_G4 */ |
| <STM32_PINMUX('G', 0, AF14)>, /* LCD_G5 */ |
| <STM32_PINMUX('C', 7, AF14)>, /* LCD_G6 */ |
| <STM32_PINMUX('A', 15, AF11)>, /* LCD_G7 */ |
| <STM32_PINMUX('D', 10, AF14)>, /* LCD_B2 */ |
| <STM32_PINMUX('F', 2, AF14)>, /* LCD_B3 */ |
| <STM32_PINMUX('H', 14, AF11)>, /* LCD_B4 */ |
| <STM32_PINMUX('E', 0, AF14)>, /* LCD_B5 */ |
| <STM32_PINMUX('B', 6, AF7)>, /* LCD_B6 */ |
| <STM32_PINMUX('F', 1, AF13)>; /* LCD_B7 */ |
| bias-disable; |
| drive-push-pull; |
| slew-rate = <0>; |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| ltdc_sleep_pins_a: ltdc-sleep-0 { |
| pins { |
| pinmux = <STM32_PINMUX('D', 9, ANALOG)>, /* LCD_CLK */ |
| <STM32_PINMUX('C', 6, ANALOG)>, /* LCD_HSYNC */ |
| <STM32_PINMUX('G', 4, ANALOG)>, /* LCD_VSYNC */ |
| <STM32_PINMUX('H', 9, ANALOG)>, /* LCD_DE */ |
| <STM32_PINMUX('G', 7, ANALOG)>, /* LCD_R2 */ |
| <STM32_PINMUX('B', 12, ANALOG)>, /* LCD_R3 */ |
| <STM32_PINMUX('D', 14, ANALOG)>, /* LCD_R4 */ |
| <STM32_PINMUX('E', 7, ANALOG)>, /* LCD_R5 */ |
| <STM32_PINMUX('E', 13, ANALOG)>, /* LCD_R6 */ |
| <STM32_PINMUX('E', 9, ANALOG)>, /* LCD_R7 */ |
| <STM32_PINMUX('H', 13, ANALOG)>, /* LCD_G2 */ |
| <STM32_PINMUX('F', 3, ANALOG)>, /* LCD_G3 */ |
| <STM32_PINMUX('D', 5, ANALOG)>, /* LCD_G4 */ |
| <STM32_PINMUX('G', 0, ANALOG)>, /* LCD_G5 */ |
| <STM32_PINMUX('C', 7, ANALOG)>, /* LCD_G6 */ |
| <STM32_PINMUX('A', 15, ANALOG)>, /* LCD_G7 */ |
| <STM32_PINMUX('D', 10, ANALOG)>, /* LCD_B2 */ |
| <STM32_PINMUX('F', 2, ANALOG)>, /* LCD_B3 */ |
| <STM32_PINMUX('H', 14, ANALOG)>, /* LCD_B4 */ |
| <STM32_PINMUX('E', 0, ANALOG)>, /* LCD_B5 */ |
| <STM32_PINMUX('B', 6, ANALOG)>, /* LCD_B6 */ |
| <STM32_PINMUX('F', 1, ANALOG)>; /* LCD_B7 */ |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| m_can1_pins_a: m-can1-0 { |
| pins1 { |
| pinmux = <STM32_PINMUX('G', 10, AF9)>; /* CAN1_TX */ |
| slew-rate = <1>; |
| drive-push-pull; |
| bias-disable; |
| }; |
| pins2 { |
| pinmux = <STM32_PINMUX('D', 0, AF9)>; /* CAN1_RX */ |
| bias-disable; |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| m_can1_sleep_pins_a: m_can1-sleep-0 { |
| pins { |
| pinmux = <STM32_PINMUX('G', 10, ANALOG)>, /* CAN1_TX */ |
| <STM32_PINMUX('D', 0, ANALOG)>; /* CAN1_RX */ |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| m_can2_pins_a: m-can2-0 { |
| pins1 { |
| pinmux = <STM32_PINMUX('G', 0, AF9)>; /* CAN2_TX */ |
| slew-rate = <1>; |
| drive-push-pull; |
| bias-disable; |
| }; |
| pins2 { |
| pinmux = <STM32_PINMUX('E', 0, AF9)>; /* CAN2_RX */ |
| bias-disable; |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| m_can2_sleep_pins_a: m_can2-sleep-0 { |
| pins { |
| pinmux = <STM32_PINMUX('G', 0, ANALOG)>, /* CAN2_TX */ |
| <STM32_PINMUX('E', 0, ANALOG)>; /* CAN2_RX */ |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| mcp23017_pins_a: mcp23017-0 { |
| pins { |
| pinmux = <STM32_PINMUX('G', 12, GPIO)>; |
| bias-pull-up; |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm3_pins_a: pwm3-0 { |
| pins { |
| pinmux = <STM32_PINMUX('B', 1, AF2)>; /* TIM3_CH4 */ |
| bias-pull-down; |
| drive-push-pull; |
| slew-rate = <0>; |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm3_sleep_pins_a: pwm3-sleep-0 { |
| pins { |
| pinmux = <STM32_PINMUX('B', 1, ANALOG)>; /* TIM3_CH4 */ |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm4_pins_a: pwm4-0 { |
| pins { |
| pinmux = <STM32_PINMUX('D', 13, AF2)>; /* TIM4_CH2 */ |
| bias-pull-down; |
| drive-push-pull; |
| slew-rate = <0>; |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm4_sleep_pins_a: pwm4-sleep-0 { |
| pins { |
| pinmux = <STM32_PINMUX('D', 13, ANALOG)>; /* TIM4_CH2 */ |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm5_pins_a: pwm5-0 { |
| pins { |
| pinmux = <STM32_PINMUX('H', 12, AF2)>; /* TIM5_CH3 */ |
| bias-pull-down; |
| drive-push-pull; |
| slew-rate = <0>; |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm5_sleep_pins_a: pwm5-sleep-0 { |
| pins { |
| pinmux = <STM32_PINMUX('H', 12, ANALOG)>; /* TIM5_CH3 */ |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm8_pins_a: pwm8-0 { |
| pins { |
| pinmux = <STM32_PINMUX('E', 5, AF3)>; /* TIM8_CH3 */ |
| bias-pull-down; |
| drive-push-pull; |
| slew-rate = <0>; |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm8_sleep_pins_a: pwm8-sleep-0 { |
| pins { |
| pinmux = <STM32_PINMUX('E', 5, ANALOG)>; /* TIM8_CH3 */ |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm13_pins_a: pwm13-0 { |
| pins { |
| pinmux = <STM32_PINMUX('A', 6, AF9)>; /* TIM13_CH1 */ |
| bias-pull-down; |
| drive-push-pull; |
| slew-rate = <0>; |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm13_sleep_pins_a: pwm13-sleep-0 { |
| pins { |
| pinmux = <STM32_PINMUX('A', 6, ANALOG)>; /* TIM13_CH1 */ |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm14_pins_a: pwm14-0 { |
| pins { |
| pinmux = <STM32_PINMUX('F', 9, AF9)>; /* TIM14_CH1 */ |
| bias-pull-down; |
| drive-push-pull; |
| slew-rate = <0>; |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm14_sleep_pins_a: pwm14-sleep-0 { |
| pins { |
| pinmux = <STM32_PINMUX('F', 9, ANALOG)>; /* TIM14_CH1 */ |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| qspi_clk_pins_a: qspi-clk-0 { |
| pins { |
| pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */ |
| bias-disable; |
| drive-push-pull; |
| slew-rate = <3>; |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| qspi_clk_sleep_pins_a: qspi-clk-sleep-0 { |
| pins { |
| pinmux = <STM32_PINMUX('F', 10, ANALOG)>; /* QSPI_CLK */ |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| qspi_bk1_pins_a: qspi-bk1-0 { |
| pins { |
| pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */ |
| <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */ |
| <STM32_PINMUX('D', 11, AF9)>, /* QSPI_BK1_IO2 */ |
| <STM32_PINMUX('H', 7, AF13)>; /* QSPI_BK1_IO3 */ |
| bias-disable; |
| drive-push-pull; |
| slew-rate = <1>; |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 { |
| pins { |
| pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */ |
| <STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */ |
| <STM32_PINMUX('D', 11, ANALOG)>, /* QSPI_BK1_IO2 */ |
| <STM32_PINMUX('H', 7, ANALOG)>; /* QSPI_BK1_IO3 */ |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| qspi_cs1_pins_a: qspi-cs1-0 { |
| pins { |
| pinmux = <STM32_PINMUX('B', 2, AF9)>; /* QSPI_BK1_NCS */ |
| bias-pull-up; |
| drive-push-pull; |
| slew-rate = <1>; |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| qspi_cs1_sleep_pins_a: qspi-cs1-sleep-0 { |
| pins { |
| pinmux = <STM32_PINMUX('B', 2, ANALOG)>; /* QSPI_BK1_NCS */ |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| sai1a_pins_a: sai1a-0 { |
| pins { |
| pinmux = <STM32_PINMUX('A', 4, AF12)>, /* SAI1_SCK_A */ |
| <STM32_PINMUX('D', 6, AF6)>, /* SAI1_SD_A */ |
| <STM32_PINMUX('E', 11, AF6)>; /* SAI1_FS_A */ |
| slew-rate = <0>; |
| drive-push-pull; |
| bias-disable; |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| sai1a_sleep_pins_a: sai1a-sleep-0 { |
| pins { |
| pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* SAI1_SCK_A */ |
| <STM32_PINMUX('D', 6, ANALOG)>, /* SAI1_SD_A */ |
| <STM32_PINMUX('E', 11, ANALOG)>; /* SAI1_FS_A */ |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| sai1b_pins_a: sai1b-0 { |
| pins { |
| pinmux = <STM32_PINMUX('A', 0, AF6)>; /* SAI1_SD_B */ |
| bias-disable; |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| sai1b_sleep_pins_a: sai1b-sleep-0 { |
| pins { |
| pinmux = <STM32_PINMUX('A', 0, ANALOG)>; /* SAI1_SD_B */ |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| sdmmc1_b4_pins_a: sdmmc1-b4-0 { |
| pins { |
| pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ |
| <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */ |
| <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */ |
| <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */ |
| <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */ |
| slew-rate = <1>; |
| drive-push-pull; |
| bias-disable; |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 { |
| pins1 { |
| pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ |
| <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */ |
| <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */ |
| <STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */ |
| slew-rate = <1>; |
| drive-push-pull; |
| bias-disable; |
| }; |
| pins2 { |
| pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */ |
| slew-rate = <1>; |
| drive-open-drain; |
| bias-disable; |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 { |
| pins { |
| pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */ |
| <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */ |
| <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */ |
| <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */ |
| <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */ |
| <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */ |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| sdmmc1_clk_pins_a: sdmmc1-clk-0 { |
| pins { |
| pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */ |
| slew-rate = <1>; |
| drive-push-pull; |
| bias-disable; |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| sdmmc2_b4_pins_a: sdmmc2-b4-0 { |
| pins { |
| pinmux = <STM32_PINMUX('B', 14, AF10)>, /* SDMMC2_D0 */ |
| <STM32_PINMUX('B', 15, AF10)>, /* SDMMC2_D1 */ |
| <STM32_PINMUX('B', 3, AF10)>, /* SDMMC2_D2 */ |
| <STM32_PINMUX('B', 4, AF10)>, /* SDMMC2_D3 */ |
| <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ |
| slew-rate = <1>; |
| drive-push-pull; |
| bias-pull-up; |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 { |
| pins1 { |
| pinmux = <STM32_PINMUX('B', 14, AF10)>, /* SDMMC2_D0 */ |
| <STM32_PINMUX('B', 15, AF10)>, /* SDMMC2_D1 */ |
| <STM32_PINMUX('B', 3, AF10)>, /* SDMMC2_D2 */ |
| <STM32_PINMUX('B', 4, AF10)>; /* SDMMC2_D3 */ |
| slew-rate = <1>; |
| drive-push-pull; |
| bias-pull-up; |
| }; |
| pins2 { |
| pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ |
| slew-rate = <1>; |
| drive-open-drain; |
| bias-pull-up; |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 { |
| pins { |
| pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC2_D0 */ |
| <STM32_PINMUX('B', 15, ANALOG)>, /* SDMMC2_D1 */ |
| <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2_D2 */ |
| <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2_D3 */ |
| <STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC2_CK */ |
| <STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */ |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| sdmmc2_clk_pins_a: sdmmc2-clk-0 { |
| pins { |
| pinmux = <STM32_PINMUX('E', 3, AF10)>; /* SDMMC2_CK */ |
| slew-rate = <1>; |
| drive-push-pull; |
| bias-pull-up; |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| sdmmc2_d47_pins_a: sdmmc2-d47-0 { |
| pins { |
| pinmux = <STM32_PINMUX('F', 0, AF10)>, /* SDMMC2_D4 */ |
| <STM32_PINMUX('B', 9, AF10)>, /* SDMMC2_D5 */ |
| <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */ |
| <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */ |
| slew-rate = <1>; |
| drive-push-pull; |
| bias-pull-up; |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 { |
| pins { |
| pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* SDMMC2_D4 */ |
| <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC2_D5 */ |
| <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */ |
| <STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */ |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| spi2_pins_a: spi2-0 { |
| pins1 { |
| pinmux = <STM32_PINMUX('B', 10, AF6)>, /* SPI2_SCK */ |
| <STM32_PINMUX('H', 10, AF6)>; /* SPI2_MOSI */ |
| bias-disable; |
| drive-push-pull; |
| slew-rate = <1>; |
| }; |
| |
| pins2 { |
| pinmux = <STM32_PINMUX('B', 5, AF5)>; /* SPI2_MISO */ |
| bias-disable; |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| spi2_sleep_pins_a: spi2-sleep-0 { |
| pins { |
| pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* SPI2_SCK */ |
| <STM32_PINMUX('B', 5, ANALOG)>, /* SPI2_MISO */ |
| <STM32_PINMUX('H', 10, ANALOG)>; /* SPI2_MOSI */ |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| spi3_pins_a: spi3-0 { |
| pins1 { |
| pinmux = <STM32_PINMUX('H', 13, AF6)>, /* SPI3_SCK */ |
| <STM32_PINMUX('F', 1, AF5)>; /* SPI3_MOSI */ |
| bias-disable; |
| drive-push-pull; |
| slew-rate = <1>; |
| }; |
| |
| pins2 { |
| pinmux = <STM32_PINMUX('D', 4, AF5)>; /* SPI3_MISO */ |
| bias-disable; |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| spi3_sleep_pins_a: spi3-sleep-0 { |
| pins { |
| pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* SPI3_SCK */ |
| <STM32_PINMUX('D', 4, ANALOG)>, /* SPI3_MISO */ |
| <STM32_PINMUX('F', 1, ANALOG)>; /* SPI3_MOSI */ |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| spi5_pins_a: spi5-0 { |
| pins1 { |
| pinmux = <STM32_PINMUX('H', 7, AF6)>, /* SPI5_SCK */ |
| <STM32_PINMUX('H', 3, AF5)>; /* SPI5_MOSI */ |
| bias-disable; |
| drive-push-pull; |
| slew-rate = <1>; |
| }; |
| |
| pins2 { |
| pinmux = <STM32_PINMUX('A', 8, AF5)>; /* SPI5_MISO */ |
| bias-disable; |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| spi5_sleep_pins_a: spi5-sleep-0 { |
| pins { |
| pinmux = <STM32_PINMUX('H', 7, ANALOG)>, /* SPI5_SCK */ |
| <STM32_PINMUX('A', 8, ANALOG)>, /* SPI5_MISO */ |
| <STM32_PINMUX('H', 3, ANALOG)>; /* SPI5_MOSI */ |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| stm32g0_intn_pins_a: stm32g0-intn-0 { |
| pins { |
| pinmux = <STM32_PINMUX('I', 2, GPIO)>; |
| bias-pull-up; |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| uart4_pins_a: uart4-0 { |
| pins1 { |
| pinmux = <STM32_PINMUX('D', 6, AF8)>; /* UART4_TX */ |
| bias-disable; |
| drive-push-pull; |
| slew-rate = <0>; |
| }; |
| pins2 { |
| pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */ |
| bias-disable; |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| uart4_idle_pins_a: uart4-idle-0 { |
| pins1 { |
| pinmux = <STM32_PINMUX('D', 6, ANALOG)>; /* UART4_TX */ |
| }; |
| pins2 { |
| pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */ |
| bias-disable; |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| uart4_sleep_pins_a: uart4-sleep-0 { |
| pins { |
| pinmux = <STM32_PINMUX('D', 6, ANALOG)>, /* UART4_TX */ |
| <STM32_PINMUX('D', 8, ANALOG)>; /* UART4_RX */ |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| uart4_pins_b: uart4-1 { |
| pins1 { |
| pinmux = <STM32_PINMUX('A', 9, AF8)>; /* UART4_TX */ |
| bias-disable; |
| drive-push-pull; |
| slew-rate = <0>; |
| }; |
| pins2 { |
| pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */ |
| bias-pull-up; |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| uart4_idle_pins_b: uart4-idle-1 { |
| pins1 { |
| pinmux = <STM32_PINMUX('A', 9, ANALOG)>; /* UART4_TX */ |
| }; |
| pins2 { |
| pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */ |
| bias-pull-up; |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| uart4_sleep_pins_b: uart4-sleep-1 { |
| pins { |
| pinmux = <STM32_PINMUX('A', 9, ANALOG)>, /* UART4_TX */ |
| <STM32_PINMUX('D', 8, ANALOG)>; /* UART4_RX */ |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| uart7_pins_a: uart7-0 { |
| pins1 { |
| pinmux = <STM32_PINMUX('H', 2, AF8)>, /* UART7_TX */ |
| <STM32_PINMUX('B', 12, AF7)>; /* UART7_RTS */ |
| bias-disable; |
| drive-push-pull; |
| slew-rate = <0>; |
| }; |
| pins2 { |
| pinmux = <STM32_PINMUX('E', 10, AF7)>, /* UART7_RX */ |
| <STM32_PINMUX('G', 7, AF8)>; /* UART7_CTS_NSS */ |
| bias-disable; |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| uart7_idle_pins_a: uart7-idle-0 { |
| pins1 { |
| pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* UART7_TX */ |
| <STM32_PINMUX('G', 7, ANALOG)>; /* UART7_CTS_NSS */ |
| }; |
| pins2 { |
| pinmux = <STM32_PINMUX('B', 12, AF7)>; /* UART7_RTS */ |
| bias-disable; |
| drive-push-pull; |
| slew-rate = <0>; |
| }; |
| pins3 { |
| pinmux = <STM32_PINMUX('E', 10, AF7)>; /* UART7_RX */ |
| bias-disable; |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| uart7_sleep_pins_a: uart7-sleep-0 { |
| pins { |
| pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* UART7_TX */ |
| <STM32_PINMUX('B', 12, ANALOG)>, /* UART7_RTS */ |
| <STM32_PINMUX('E', 10, ANALOG)>, /* UART7_RX */ |
| <STM32_PINMUX('G', 7, ANALOG)>; /* UART7_CTS_NSS */ |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| uart8_pins_a: uart8-0 { |
| pins1 { |
| pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */ |
| bias-disable; |
| drive-push-pull; |
| slew-rate = <0>; |
| }; |
| pins2 { |
| pinmux = <STM32_PINMUX('F', 9, AF8)>; /* UART8_RX */ |
| bias-pull-up; |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| uart8_idle_pins_a: uart8-idle-0 { |
| pins1 { |
| pinmux = <STM32_PINMUX('E', 1, ANALOG)>; /* UART8_TX */ |
| }; |
| pins2 { |
| pinmux = <STM32_PINMUX('F', 9, AF8)>; /* UART8_RX */ |
| bias-pull-up; |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| uart8_sleep_pins_a: uart8-sleep-0 { |
| pins { |
| pinmux = <STM32_PINMUX('E', 1, ANALOG)>, /* UART8_TX */ |
| <STM32_PINMUX('F', 9, ANALOG)>; /* UART8_RX */ |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| usart1_pins_a: usart1-0 { |
| pins1 { |
| pinmux = <STM32_PINMUX('C', 0, AF7)>, /* USART1_TX */ |
| <STM32_PINMUX('C', 2, AF7)>; /* USART1_RTS */ |
| bias-disable; |
| drive-push-pull; |
| slew-rate = <0>; |
| }; |
| pins2 { |
| pinmux = <STM32_PINMUX('B', 0, AF4)>, /* USART1_RX */ |
| <STM32_PINMUX('A', 7, AF7)>; /* USART1_CTS_NSS */ |
| bias-pull-up; |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| usart1_idle_pins_a: usart1-idle-0 { |
| pins1 { |
| pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* USART1_TX */ |
| <STM32_PINMUX('A', 7, ANALOG)>; /* USART1_CTS_NSS */ |
| }; |
| pins2 { |
| pinmux = <STM32_PINMUX('C', 2, AF7)>; /* USART1_RTS */ |
| bias-disable; |
| drive-push-pull; |
| slew-rate = <0>; |
| }; |
| pins3 { |
| pinmux = <STM32_PINMUX('B', 0, AF4)>; /* USART1_RX */ |
| bias-pull-up; |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| usart1_sleep_pins_a: usart1-sleep-0 { |
| pins { |
| pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* USART1_TX */ |
| <STM32_PINMUX('C', 2, ANALOG)>, /* USART1_RTS */ |
| <STM32_PINMUX('A', 7, ANALOG)>, /* USART1_CTS_NSS */ |
| <STM32_PINMUX('B', 0, ANALOG)>; /* USART1_RX */ |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| usart1_pins_b: usart1-1 { |
| pins1 { |
| pinmux = <STM32_PINMUX('C', 0, AF7)>; /* USART1_TX */ |
| bias-disable; |
| drive-push-pull; |
| slew-rate = <0>; |
| }; |
| pins2 { |
| pinmux = <STM32_PINMUX('D', 14, AF7)>; /* USART1_RX */ |
| bias-pull-up; |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| usart1_idle_pins_b: usart1-idle-1 { |
| pins1 { |
| pinmux = <STM32_PINMUX('C', 0, ANALOG)>; /* USART1_TX */ |
| }; |
| pins2 { |
| pinmux = <STM32_PINMUX('D', 14, AF7)>; /* USART1_RX */ |
| bias-pull-up; |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| usart1_sleep_pins_b: usart1-sleep-1 { |
| pins { |
| pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* USART1_TX */ |
| <STM32_PINMUX('D', 14, ANALOG)>; /* USART1_RX */ |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| usart2_pins_a: usart2-0 { |
| pins1 { |
| pinmux = <STM32_PINMUX('H', 12, AF1)>, /* USART2_TX */ |
| <STM32_PINMUX('D', 4, AF3)>; /* USART2_RTS */ |
| bias-disable; |
| drive-push-pull; |
| slew-rate = <0>; |
| }; |
| pins2 { |
| pinmux = <STM32_PINMUX('D', 15, AF1)>, /* USART2_RX */ |
| <STM32_PINMUX('E', 11, AF2)>; /* USART2_CTS_NSS */ |
| bias-disable; |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| usart2_idle_pins_a: usart2-idle-0 { |
| pins1 { |
| pinmux = <STM32_PINMUX('H', 12, ANALOG)>, /* USART2_TX */ |
| <STM32_PINMUX('E', 11, ANALOG)>; /* USART2_CTS_NSS */ |
| }; |
| pins2 { |
| pinmux = <STM32_PINMUX('D', 4, AF3)>; /* USART2_RTS */ |
| bias-disable; |
| drive-push-pull; |
| slew-rate = <0>; |
| }; |
| pins3 { |
| pinmux = <STM32_PINMUX('D', 15, AF1)>; /* USART2_RX */ |
| bias-disable; |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| usart2_sleep_pins_a: usart2-sleep-0 { |
| pins { |
| pinmux = <STM32_PINMUX('H', 12, ANALOG)>, /* USART2_TX */ |
| <STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */ |
| <STM32_PINMUX('D', 15, ANALOG)>, /* USART2_RX */ |
| <STM32_PINMUX('E', 11, ANALOG)>; /* USART2_CTS_NSS */ |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| usart2_pins_b: usart2-1 { |
| pins1 { |
| pinmux = <STM32_PINMUX('F', 11, AF1)>, /* USART2_TX */ |
| <STM32_PINMUX('A', 1, AF7)>; /* USART2_RTS */ |
| bias-disable; |
| drive-push-pull; |
| slew-rate = <0>; |
| }; |
| pins2 { |
| pinmux = <STM32_PINMUX('D', 15, AF1)>, /* USART2_RX */ |
| <STM32_PINMUX('E', 15, AF3)>; /* USART2_CTS_NSS */ |
| bias-disable; |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| usart2_idle_pins_b: usart2-idle-1 { |
| pins1 { |
| pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* USART2_TX */ |
| <STM32_PINMUX('E', 15, ANALOG)>; /* USART2_CTS_NSS */ |
| }; |
| pins2 { |
| pinmux = <STM32_PINMUX('A', 1, AF7)>; /* USART2_RTS */ |
| bias-disable; |
| drive-push-pull; |
| slew-rate = <0>; |
| }; |
| pins3 { |
| pinmux = <STM32_PINMUX('D', 15, AF1)>; /* USART2_RX */ |
| bias-disable; |
| }; |
| }; |
| |
| /omit-if-no-ref/ |
| usart2_sleep_pins_b: usart2-sleep-1 { |
| pins { |
| pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* USART2_TX */ |
| <STM32_PINMUX('A', 1, ANALOG)>, /* USART2_RTS */ |
| <STM32_PINMUX('D', 15, ANALOG)>, /* USART2_RX */ |
| <STM32_PINMUX('E', 15, ANALOG)>; /* USART2_CTS_NSS */ |
| }; |
| }; |
| }; |
