| Binding for the AXS10X Generic PLL clock |
| This binding uses the common clock binding[1]. |
| [1] Documentation/devicetree/bindings/clock/clock-bindings.txt |
| - compatible: should be "snps,axs10x-<name>-pll-clock" |
| "snps,axs10x-arc-pll-clock" |
| "snps,axs10x-pgu-pll-clock" |
| - reg: should always contain 2 pairs address - length: first for PLL config |
| registers and second for corresponding LOCK CGU register. |
| - clocks: shall be the input parent clock phandle for the PLL. |
| - #clock-cells: from common clock binding; Should always be set to 0. |
| clock-frequency = <33333333>; |
| compatible = "fixed-clock"; |
| compatible = "snps,axs10x-arc-pll-clock"; |
| reg = <0x80 0x10>, <0x100 0x10>; |