blob: 183b1ec8b1f0f7be1100803c8931a8bd5a4d37dc [file] [log] [blame]
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
* Copyright (C) 2020 Marvell International Ltd.
* Device tree for the CN9131-DB board (setup "B").
#include "cn9131-db.dtsi"
/ {
model = "Marvell Armada CN9131-DB setup B";
/* Setup B has NAND flash as a boot device, while regular setup uses SPI flash.
* Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
* simultaneously. When NAND controller is enabled, SPI1 should be disabled.
&cp0_nand_controller {
status = "okay";