| [ |
| { |
| "BriefDescription": "This event counts the cycles the floating point divider is busy.", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "CounterMask": "1", |
| "EventCode": "0xb0", |
| "EventName": "ARITH.FPDIV_ACTIVE", |
| "SampleAfterValue": "1000003", |
| "UMask": "0x1" |
| }, |
| { |
| "BriefDescription": "Counts all microcode FP assists.", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xc1", |
| "EventName": "ASSISTS.FP", |
| "PublicDescription": "Counts all microcode Floating Point assists.", |
| "SampleAfterValue": "100003", |
| "UMask": "0x2" |
| }, |
| { |
| "BriefDescription": "ASSISTS.SSE_AVX_MIX", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xc1", |
| "EventName": "ASSISTS.SSE_AVX_MIX", |
| "SampleAfterValue": "1000003", |
| "UMask": "0x10" |
| }, |
| { |
| "BriefDescription": "FP_ARITH_DISPATCHED.PORT_0 [This event is alias to FP_ARITH_DISPATCHED.V0]", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xb3", |
| "EventName": "FP_ARITH_DISPATCHED.PORT_0", |
| "SampleAfterValue": "2000003", |
| "UMask": "0x1" |
| }, |
| { |
| "BriefDescription": "FP_ARITH_DISPATCHED.PORT_1 [This event is alias to FP_ARITH_DISPATCHED.V1]", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xb3", |
| "EventName": "FP_ARITH_DISPATCHED.PORT_1", |
| "SampleAfterValue": "2000003", |
| "UMask": "0x2" |
| }, |
| { |
| "BriefDescription": "FP_ARITH_DISPATCHED.PORT_5 [This event is alias to FP_ARITH_DISPATCHED.V2]", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xb3", |
| "EventName": "FP_ARITH_DISPATCHED.PORT_5", |
| "SampleAfterValue": "2000003", |
| "UMask": "0x4" |
| }, |
| { |
| "BriefDescription": "FP_ARITH_DISPATCHED.V0 [This event is alias to FP_ARITH_DISPATCHED.PORT_0]", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xb3", |
| "EventName": "FP_ARITH_DISPATCHED.V0", |
| "SampleAfterValue": "2000003", |
| "UMask": "0x1" |
| }, |
| { |
| "BriefDescription": "FP_ARITH_DISPATCHED.V1 [This event is alias to FP_ARITH_DISPATCHED.PORT_1]", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xb3", |
| "EventName": "FP_ARITH_DISPATCHED.V1", |
| "SampleAfterValue": "2000003", |
| "UMask": "0x2" |
| }, |
| { |
| "BriefDescription": "FP_ARITH_DISPATCHED.V2 [This event is alias to FP_ARITH_DISPATCHED.PORT_5]", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xb3", |
| "EventName": "FP_ARITH_DISPATCHED.V2", |
| "SampleAfterValue": "2000003", |
| "UMask": "0x4" |
| }, |
| { |
| "BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xc7", |
| "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", |
| "PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", |
| "SampleAfterValue": "100003", |
| "UMask": "0x4" |
| }, |
| { |
| "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xc7", |
| "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", |
| "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", |
| "SampleAfterValue": "100003", |
| "UMask": "0x8" |
| }, |
| { |
| "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xc7", |
| "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", |
| "PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", |
| "SampleAfterValue": "100003", |
| "UMask": "0x10" |
| }, |
| { |
| "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xc7", |
| "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", |
| "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", |
| "SampleAfterValue": "100003", |
| "UMask": "0x20" |
| }, |
| { |
| "BriefDescription": "Number of SSE/AVX computational 128-bit packed single and 256-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and packed double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xc7", |
| "EventName": "FP_ARITH_INST_RETIRED.4_FLOPS", |
| "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision and 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", |
| "SampleAfterValue": "100003", |
| "UMask": "0x18" |
| }, |
| { |
| "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xc7", |
| "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE", |
| "PublicDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", |
| "SampleAfterValue": "100003", |
| "UMask": "0x40" |
| }, |
| { |
| "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xc7", |
| "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", |
| "PublicDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", |
| "SampleAfterValue": "100003", |
| "UMask": "0x80" |
| }, |
| { |
| "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision and 512-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xc7", |
| "EventName": "FP_ARITH_INST_RETIRED.8_FLOPS", |
| "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision and 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision and double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", |
| "SampleAfterValue": "100003", |
| "UMask": "0x60" |
| }, |
| { |
| "BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xc7", |
| "EventName": "FP_ARITH_INST_RETIRED.SCALAR", |
| "PublicDescription": "Number of SSE/AVX computational scalar single precision and double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", |
| "SampleAfterValue": "1000003", |
| "UMask": "0x3" |
| }, |
| { |
| "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xc7", |
| "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", |
| "PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", |
| "SampleAfterValue": "100003", |
| "UMask": "0x1" |
| }, |
| { |
| "BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xc7", |
| "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", |
| "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", |
| "SampleAfterValue": "100003", |
| "UMask": "0x2" |
| }, |
| { |
| "BriefDescription": "Number of any Vector retired FP arithmetic instructions", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xc7", |
| "EventName": "FP_ARITH_INST_RETIRED.VECTOR", |
| "PublicDescription": "Number of any Vector retired FP arithmetic instructions. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", |
| "SampleAfterValue": "1000003", |
| "UMask": "0xfc" |
| }, |
| { |
| "BriefDescription": "FP_ARITH_INST_RETIRED2.128B_PACKED_HALF", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xcf", |
| "EventName": "FP_ARITH_INST_RETIRED2.128B_PACKED_HALF", |
| "SampleAfterValue": "100003", |
| "UMask": "0x4" |
| }, |
| { |
| "BriefDescription": "FP_ARITH_INST_RETIRED2.256B_PACKED_HALF", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xcf", |
| "EventName": "FP_ARITH_INST_RETIRED2.256B_PACKED_HALF", |
| "SampleAfterValue": "100003", |
| "UMask": "0x8" |
| }, |
| { |
| "BriefDescription": "FP_ARITH_INST_RETIRED2.512B_PACKED_HALF", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xcf", |
| "EventName": "FP_ARITH_INST_RETIRED2.512B_PACKED_HALF", |
| "SampleAfterValue": "100003", |
| "UMask": "0x10" |
| }, |
| { |
| "BriefDescription": "FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xcf", |
| "EventName": "FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF", |
| "SampleAfterValue": "100003", |
| "UMask": "0x2" |
| }, |
| { |
| "BriefDescription": "Number of all Scalar Half-Precision FP arithmetic instructions(1) retired - regular and complex.", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xcf", |
| "EventName": "FP_ARITH_INST_RETIRED2.SCALAR", |
| "PublicDescription": "FP_ARITH_INST_RETIRED2.SCALAR", |
| "SampleAfterValue": "100003", |
| "UMask": "0x3" |
| }, |
| { |
| "BriefDescription": "FP_ARITH_INST_RETIRED2.SCALAR_HALF", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xcf", |
| "EventName": "FP_ARITH_INST_RETIRED2.SCALAR_HALF", |
| "SampleAfterValue": "100003", |
| "UMask": "0x1" |
| }, |
| { |
| "BriefDescription": "Number of all Vector (also called packed) Half-Precision FP arithmetic instructions(1) retired.", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xcf", |
| "EventName": "FP_ARITH_INST_RETIRED2.VECTOR", |
| "PublicDescription": "FP_ARITH_INST_RETIRED2.VECTOR", |
| "SampleAfterValue": "100003", |
| "UMask": "0x1c" |
| } |
| ] |
