| [ |
| { |
| "BriefDescription": "Total Write Cache Occupancy : Any Source", |
| "Counter": "0,1", |
| "EventCode": "0x0F", |
| "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Total Write Cache Occupancy : Any Source : Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events. : Tracks all requests from any source port.", |
| "UMask": "0x1", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": "Total Write Cache Occupancy : Snoops", |
| "Counter": "0,1", |
| "EventCode": "0x0F", |
| "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.IV_Q", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Total Write Cache Occupancy : Snoops : Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.", |
| "UMask": "0x2", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": "Total IRP occupancy of inbound read and write requests to coherent memory.", |
| "Counter": "0,1", |
| "EventCode": "0x0f", |
| "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.MEM", |
| "PerPkg": "1", |
| "PublicDescription": "Total IRP occupancy of inbound read and write requests to coherent memory. This is effectively the sum of read occupancy and write occupancy.", |
| "UMask": "0x4", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": "Clockticks of the IO coherency tracker (IRP)", |
| "Counter": "0,1", |
| "EventCode": "0x01", |
| "EventName": "UNC_I_CLOCKTICKS", |
| "PerPkg": "1", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": "Coherent Ops : CLFlush", |
| "Counter": "0,1", |
| "EventCode": "0x10", |
| "EventName": "UNC_I_COHERENT_OPS.CLFLUSH", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Coherent Ops : CLFlush : Counts the number of coherency related operations serviced by the IRP", |
| "UMask": "0x80", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline.", |
| "Counter": "0,1", |
| "EventCode": "0x10", |
| "EventName": "UNC_I_COHERENT_OPS.PCITOM", |
| "PerPkg": "1", |
| "PublicDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline to coherent memory, without a RFO. PCIITOM is a speculative Invalidate to Modified command that requests ownership of the cacheline and does not move data from the mesh to IRP cache.", |
| "UMask": "0x10", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": "RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline.", |
| "Counter": "0,1", |
| "EventCode": "0x10", |
| "EventName": "UNC_I_COHERENT_OPS.RFO", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline to coherent memory. RFO is a Read For Ownership command that requests ownership of the cacheline and moves data from the mesh to IRP cache.", |
| "UMask": "0x8", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": "Coherent Ops : WbMtoI", |
| "Counter": "0,1", |
| "EventCode": "0x10", |
| "EventName": "UNC_I_COHERENT_OPS.WBMTOI", |
| "PerPkg": "1", |
| "PublicDescription": "Coherent Ops : WbMtoI : Counts the number of coherency related operations serviced by the IRP", |
| "UMask": "0x40", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": "FAF RF full", |
| "Counter": "0,1", |
| "EventCode": "0x17", |
| "EventName": "UNC_I_FAF_FULL", |
| "PerPkg": "1", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": "Inbound read requests received by the IRP and inserted into the FAF queue.", |
| "Counter": "0,1", |
| "EventCode": "0x18", |
| "EventName": "UNC_I_FAF_INSERTS", |
| "PerPkg": "1", |
| "PublicDescription": "Inbound read requests to coherent memory, received by the IRP and inserted into the Fire and Forget queue (FAF), a queue used for processing inbound reads in the IRP.", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": "Occupancy of the IRP FAF queue.", |
| "Counter": "0,1", |
| "EventCode": "0x19", |
| "EventName": "UNC_I_FAF_OCCUPANCY", |
| "PerPkg": "1", |
| "PublicDescription": "Occupancy of the IRP Fire and Forget (FAF) queue, a queue used for processing inbound reads in the IRP.", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": "FAF allocation -- sent to ADQ", |
| "Counter": "0,1", |
| "EventCode": "0x16", |
| "EventName": "UNC_I_FAF_TRANSACTIONS", |
| "PerPkg": "1", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": ": All Inserts Outbound (BL, AK, Snoops)", |
| "Counter": "0,1", |
| "EventCode": "0x20", |
| "EventName": "UNC_I_IRP_ALL.EVICTS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x4", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": ": All Inserts Inbound (p2p + faf + cset)", |
| "Counter": "0,1", |
| "EventCode": "0x20", |
| "EventName": "UNC_I_IRP_ALL.INBOUND_INSERTS", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": ": All Inserts Outbound (BL, AK, Snoops)", |
| "Counter": "0,1", |
| "EventCode": "0x20", |
| "EventName": "UNC_I_IRP_ALL.OUTBOUND_INSERTS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Atomic Transactions as Secondary", |
| "Counter": "0,1", |
| "EventCode": "0x1E", |
| "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x10", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Read Transactions as Secondary", |
| "Counter": "0,1", |
| "EventCode": "0x1e", |
| "EventName": "UNC_I_MISC0.2ND_RD_INSERT", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x4", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Write Transactions as Secondary", |
| "Counter": "0,1", |
| "EventCode": "0x1e", |
| "EventName": "UNC_I_MISC0.2ND_WR_INSERT", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x8", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Rejects", |
| "Counter": "0,1", |
| "EventCode": "0x1E", |
| "EventName": "UNC_I_MISC0.FAST_REJ", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Requests", |
| "Counter": "0,1", |
| "EventCode": "0x1e", |
| "EventName": "UNC_I_MISC0.FAST_REQ", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Transfers From Primary to Secondary", |
| "Counter": "0,1", |
| "EventCode": "0x1E", |
| "EventName": "UNC_I_MISC0.FAST_XFER", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x20", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": "Counts Timeouts - Set 0 : Prefetch Ack Hints From Primary to Secondary", |
| "Counter": "0,1", |
| "EventCode": "0x1E", |
| "EventName": "UNC_I_MISC0.PF_ACK_HINT", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x40", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": "Counts Timeouts - Set 0 : Slow path fwpf didn't find prefetch", |
| "Counter": "0,1", |
| "EventCode": "0x1E", |
| "EventName": "UNC_I_MISC0.SLOWPATH_FWPF_NO_PRF", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x80", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": "Misc Events - Set 1 : Lost Forward", |
| "Counter": "0,1", |
| "EventCode": "0x1F", |
| "EventName": "UNC_I_MISC1.LOST_FWD", |
| "PerPkg": "1", |
| "PublicDescription": "Misc Events - Set 1 : Lost Forward : Snoop pulled away ownership before a write was committed", |
| "UMask": "0x10", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": "Misc Events - Set 1 : Received Invalid", |
| "Counter": "0,1", |
| "EventCode": "0x1F", |
| "EventName": "UNC_I_MISC1.SEC_RCVD_INVLD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Misc Events - Set 1 : Received Invalid : Secondary received a transfer that did not have sufficient MESI state", |
| "UMask": "0x20", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": "Misc Events - Set 1 : Received Valid", |
| "Counter": "0,1", |
| "EventCode": "0x1F", |
| "EventName": "UNC_I_MISC1.SEC_RCVD_VLD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Misc Events - Set 1 : Received Valid : Secondary received a transfer that did have sufficient MESI state", |
| "UMask": "0x40", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": "Misc Events - Set 1 : Slow Transfer of E Line", |
| "Counter": "0,1", |
| "EventCode": "0x1f", |
| "EventName": "UNC_I_MISC1.SLOW_E", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Misc Events - Set 1 : Slow Transfer of E Line : Secondary received a transfer that did have sufficient MESI state", |
| "UMask": "0x4", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": "Misc Events - Set 1 : Slow Transfer of I Line", |
| "Counter": "0,1", |
| "EventCode": "0x1f", |
| "EventName": "UNC_I_MISC1.SLOW_I", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Misc Events - Set 1 : Slow Transfer of I Line : Snoop took cacheline ownership before write from data was committed.", |
| "UMask": "0x1", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": "Misc Events - Set 1 : Slow Transfer of M Line", |
| "Counter": "0,1", |
| "EventCode": "0x1f", |
| "EventName": "UNC_I_MISC1.SLOW_M", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Misc Events - Set 1 : Slow Transfer of M Line : Snoop took cacheline ownership before write from data was committed.", |
| "UMask": "0x8", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": "Misc Events - Set 1 : Slow Transfer of S Line", |
| "Counter": "0,1", |
| "EventCode": "0x1f", |
| "EventName": "UNC_I_MISC1.SLOW_S", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Misc Events - Set 1 : Slow Transfer of S Line : Secondary received a transfer that did not have sufficient MESI state", |
| "UMask": "0x2", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": "P2P Requests", |
| "Counter": "0,1", |
| "EventCode": "0x14", |
| "EventName": "UNC_I_P2P_INSERTS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "P2P Requests : P2P requests from the ITC", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": "P2P Occupancy", |
| "Counter": "0,1", |
| "EventCode": "0x15", |
| "EventName": "UNC_I_P2P_OCCUPANCY", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "P2P Occupancy : P2P B & S Queue Occupancy", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": "P2P Transactions : P2P completions", |
| "Counter": "0,1", |
| "EventCode": "0x13", |
| "EventName": "UNC_I_P2P_TRANSACTIONS.CMPL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x8", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": "P2P Transactions : match if local only", |
| "Counter": "0,1", |
| "EventCode": "0x13", |
| "EventName": "UNC_I_P2P_TRANSACTIONS.LOC", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x40", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": "P2P Transactions : match if local and target matches", |
| "Counter": "0,1", |
| "EventCode": "0x13", |
| "EventName": "UNC_I_P2P_TRANSACTIONS.LOC_AND_TGT_MATCH", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x80", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": "P2P Transactions : P2P Message", |
| "Counter": "0,1", |
| "EventCode": "0x13", |
| "EventName": "UNC_I_P2P_TRANSACTIONS.MSG", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x4", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": "P2P Transactions : P2P reads", |
| "Counter": "0,1", |
| "EventCode": "0x13", |
| "EventName": "UNC_I_P2P_TRANSACTIONS.RD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": "P2P Transactions : Match if remote only", |
| "Counter": "0,1", |
| "EventCode": "0x13", |
| "EventName": "UNC_I_P2P_TRANSACTIONS.REM", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x10", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": "P2P Transactions : match if remote and target matches", |
| "Counter": "0,1", |
| "EventCode": "0x13", |
| "EventName": "UNC_I_P2P_TRANSACTIONS.REM_AND_TGT_MATCH", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x20", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": "P2P Transactions : P2P Writes", |
| "Counter": "0,1", |
| "EventCode": "0x13", |
| "EventName": "UNC_I_P2P_TRANSACTIONS.WR", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": "Responses to snoops of any type that hit M, E, S or I line in the IIO", |
| "Counter": "0,1", |
| "EventCode": "0x12", |
| "EventName": "UNC_I_SNOOP_RESP.ALL_HIT", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit M, E, S or I line in the IIO", |
| "UMask": "0x7e", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": "Responses to snoops of any type that hit E or S line in the IIO cache", |
| "Counter": "0,1", |
| "EventCode": "0x12", |
| "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_ES", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit E or S line in the IIO cache", |
| "UMask": "0x74", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": "Responses to snoops of any type that hit I line in the IIO cache", |
| "Counter": "0,1", |
| "EventCode": "0x12", |
| "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_I", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit I line in the IIO cache", |
| "UMask": "0x72", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": "Responses to snoops of any type that hit M line in the IIO cache", |
| "Counter": "0,1", |
| "EventCode": "0x12", |
| "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_M", |
| "PerPkg": "1", |
| "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit M line in the IIO cache", |
| "UMask": "0x78", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": "Responses to snoops of any type that miss the IIO cache", |
| "Counter": "0,1", |
| "EventCode": "0x12", |
| "EventName": "UNC_I_SNOOP_RESP.ALL_MISS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that miss the IIO cache", |
| "UMask": "0x71", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": "Snoop Responses : Hit E or S", |
| "Counter": "0,1", |
| "EventCode": "0x12", |
| "EventName": "UNC_I_SNOOP_RESP.HIT_ES", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x4", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": "Snoop Responses : Hit I", |
| "Counter": "0,1", |
| "EventCode": "0x12", |
| "EventName": "UNC_I_SNOOP_RESP.HIT_I", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": "Snoop Responses : Hit M", |
| "Counter": "0,1", |
| "EventCode": "0x12", |
| "EventName": "UNC_I_SNOOP_RESP.HIT_M", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x8", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": "Snoop Responses : Miss", |
| "Counter": "0,1", |
| "EventCode": "0x12", |
| "EventName": "UNC_I_SNOOP_RESP.MISS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": "Snoop Responses : SnpCode", |
| "Counter": "0,1", |
| "EventCode": "0x12", |
| "EventName": "UNC_I_SNOOP_RESP.SNPCODE", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x10", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": "Snoop Responses : SnpData", |
| "Counter": "0,1", |
| "EventCode": "0x12", |
| "EventName": "UNC_I_SNOOP_RESP.SNPDATA", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x20", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": "Snoop Responses : SnpInv", |
| "Counter": "0,1", |
| "EventCode": "0x12", |
| "EventName": "UNC_I_SNOOP_RESP.SNPINV", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x40", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": "Inbound Transaction Count : Atomic", |
| "Counter": "0,1", |
| "EventCode": "0x11", |
| "EventName": "UNC_I_TRANSACTIONS.ATOMIC", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Inbound Transaction Count : Atomic : Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID. : Tracks the number of atomic transactions", |
| "UMask": "0x10", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": "Inbound Transaction Count : Other", |
| "Counter": "0,1", |
| "EventCode": "0x11", |
| "EventName": "UNC_I_TRANSACTIONS.OTHER", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Inbound Transaction Count : Other : Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID. : Tracks the number of 'other' kinds of transactions.", |
| "UMask": "0x20", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": "Inbound Transaction Count : Writes", |
| "Counter": "0,1", |
| "EventCode": "0x11", |
| "EventName": "UNC_I_TRANSACTIONS.WRITES", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Inbound Transaction Count : Writes : Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID. : Tracks only write requests. Each write request should have a prefetch, so there is no need to explicitly track these requests. For writes that are tickled and have to retry, the counter will be incremented for each retry.", |
| "UMask": "0x2", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": "Inbound write (fast path) requests received by the IRP.", |
| "Counter": "0,1", |
| "EventCode": "0x11", |
| "EventName": "UNC_I_TRANSACTIONS.WR_PREF", |
| "PerPkg": "1", |
| "PublicDescription": "Inbound write (fast path) requests to coherent memory, received by the IRP resulting in write ownership requests issued by IRP to the mesh.", |
| "UMask": "0x8", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": "AK Egress Allocations", |
| "Counter": "0,1", |
| "EventCode": "0x0B", |
| "EventName": "UNC_I_TxC_AK_INSERTS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": "BL DRS Egress Cycles Full", |
| "Counter": "0,1", |
| "EventCode": "0x05", |
| "EventName": "UNC_I_TxC_BL_DRS_CYCLES_FULL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": "BL DRS Egress Inserts", |
| "Counter": "0,1", |
| "EventCode": "0x02", |
| "EventName": "UNC_I_TxC_BL_DRS_INSERTS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": "BL DRS Egress Occupancy", |
| "Counter": "0,1", |
| "EventCode": "0x08", |
| "EventName": "UNC_I_TxC_BL_DRS_OCCUPANCY", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": "BL NCB Egress Cycles Full", |
| "Counter": "0,1", |
| "EventCode": "0x06", |
| "EventName": "UNC_I_TxC_BL_NCB_CYCLES_FULL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": "BL NCB Egress Inserts", |
| "Counter": "0,1", |
| "EventCode": "0x03", |
| "EventName": "UNC_I_TxC_BL_NCB_INSERTS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": "BL NCB Egress Occupancy", |
| "Counter": "0,1", |
| "EventCode": "0x09", |
| "EventName": "UNC_I_TxC_BL_NCB_OCCUPANCY", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": "BL NCS Egress Cycles Full", |
| "Counter": "0,1", |
| "EventCode": "0x07", |
| "EventName": "UNC_I_TxC_BL_NCS_CYCLES_FULL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": "BL NCS Egress Inserts", |
| "Counter": "0,1", |
| "EventCode": "0x04", |
| "EventName": "UNC_I_TxC_BL_NCS_INSERTS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": "BL NCS Egress Occupancy", |
| "Counter": "0,1", |
| "EventCode": "0x0A", |
| "EventName": "UNC_I_TxC_BL_NCS_OCCUPANCY", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": "UNC_I_TxR2_AD01_STALL_CREDIT_CYCLES", |
| "Counter": "0,1", |
| "EventCode": "0x1C", |
| "EventName": "UNC_I_TxR2_AD01_STALL_CREDIT_CYCLES", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": ": Counts the number times when it is not possible to issue a request to the M2PCIe because there are no Egress Credits available on AD0, A1 or AD0&AD1 both. Stalls on both AD0 and AD1 will count as 2", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": "No AD0 Egress Credits Stalls", |
| "Counter": "0,1", |
| "EventCode": "0x1A", |
| "EventName": "UNC_I_TxR2_AD0_STALL_CREDIT_CYCLES", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "No AD0 Egress Credits Stalls : Counts the number times when it is not possible to issue a request to the M2PCIe because there are no AD0 Egress Credits available.", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": "No AD1 Egress Credits Stalls", |
| "Counter": "0,1", |
| "EventCode": "0x1B", |
| "EventName": "UNC_I_TxR2_AD1_STALL_CREDIT_CYCLES", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "No AD1 Egress Credits Stalls : Counts the number times when it is not possible to issue a request to the M2PCIe because there are no AD1 Egress Credits available.", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": "No BL Egress Credit Stalls", |
| "Counter": "0,1", |
| "EventCode": "0x1D", |
| "EventName": "UNC_I_TxR2_BL_STALL_CREDIT_CYCLES", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "No BL Egress Credit Stalls : Counts the number times when it is not possible to issue data to the R2PCIe because there are no BL Egress Credits available.", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": "Outbound Read Requests", |
| "Counter": "0,1", |
| "EventCode": "0x0D", |
| "EventName": "UNC_I_TxS_DATA_INSERTS_NCB", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Outbound Read Requests : Counts the number of requests issued to the switch (towards the devices).", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": "Outbound Read Requests", |
| "Counter": "0,1", |
| "EventCode": "0x0E", |
| "EventName": "UNC_I_TxS_DATA_INSERTS_NCS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Outbound Read Requests : Counts the number of requests issued to the switch (towards the devices).", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": "Outbound Request Queue Occupancy", |
| "Counter": "0,1", |
| "EventCode": "0x0C", |
| "EventName": "UNC_I_TxS_REQUEST_OCCUPANCY", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Outbound Request Queue Occupancy : Accumulates the number of outstanding outbound requests from the IRP to the switch (towards the devices). This can be used in conjunction with the allocations event in order to calculate average latency of outbound requests.", |
| "Unit": "IRP" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x80", |
| "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x80", |
| "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x80", |
| "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR2", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x80", |
| "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR3", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", |
| "UMask": "0x8", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x80", |
| "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR4", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", |
| "UMask": "0x10", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x80", |
| "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR5", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", |
| "UMask": "0x20", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x80", |
| "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR6", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", |
| "UMask": "0x40", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x80", |
| "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR7", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", |
| "UMask": "0x80", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x81", |
| "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED1.TGR10", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x81", |
| "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED1.TGR8", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x81", |
| "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED1.TGR9", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x82", |
| "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x82", |
| "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x82", |
| "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR2", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x82", |
| "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR3", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", |
| "UMask": "0x8", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x82", |
| "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR4", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", |
| "UMask": "0x10", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x82", |
| "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR5", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", |
| "UMask": "0x20", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x82", |
| "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR6", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", |
| "UMask": "0x40", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x82", |
| "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR7", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", |
| "UMask": "0x80", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x83", |
| "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY1.TGR10", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x83", |
| "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY1.TGR8", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x83", |
| "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY1.TGR9", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x88", |
| "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x88", |
| "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x88", |
| "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR2", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x88", |
| "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR3", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", |
| "UMask": "0x8", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x88", |
| "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR4", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", |
| "UMask": "0x10", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x88", |
| "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR5", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", |
| "UMask": "0x20", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x88", |
| "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR6", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", |
| "UMask": "0x40", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x88", |
| "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR7", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", |
| "UMask": "0x80", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x89", |
| "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED1.TGR10", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x89", |
| "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED1.TGR8", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x89", |
| "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED1.TGR9", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8A", |
| "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8A", |
| "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8A", |
| "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR2", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8A", |
| "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR3", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", |
| "UMask": "0x8", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8A", |
| "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR4", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", |
| "UMask": "0x10", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8A", |
| "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR5", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", |
| "UMask": "0x20", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8A", |
| "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR6", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", |
| "UMask": "0x40", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8A", |
| "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR7", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", |
| "UMask": "0x80", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8B", |
| "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY1.TGR10", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8B", |
| "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY1.TGR8", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8B", |
| "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY1.TGR9", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR2", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR3", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", |
| "UMask": "0x8", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR4", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", |
| "UMask": "0x10", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR5", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", |
| "UMask": "0x20", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR6", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", |
| "UMask": "0x40", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR7", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", |
| "UMask": "0x80", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x85", |
| "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED1.TGR10", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x85", |
| "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED1.TGR8", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x85", |
| "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED1.TGR9", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x86", |
| "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x86", |
| "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x86", |
| "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR2", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x86", |
| "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR3", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", |
| "UMask": "0x8", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x86", |
| "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR4", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", |
| "UMask": "0x10", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x86", |
| "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR5", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", |
| "UMask": "0x20", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x86", |
| "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR6", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", |
| "UMask": "0x40", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x86", |
| "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR7", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", |
| "UMask": "0x80", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x87", |
| "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY1.TGR10", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x87", |
| "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY1.TGR8", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x87", |
| "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY1.TGR9", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8C", |
| "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8C", |
| "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8C", |
| "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR2", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8C", |
| "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR3", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", |
| "UMask": "0x8", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8C", |
| "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR4", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", |
| "UMask": "0x10", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8C", |
| "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR5", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", |
| "UMask": "0x20", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8C", |
| "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR6", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", |
| "UMask": "0x40", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8C", |
| "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR7", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", |
| "UMask": "0x80", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8D", |
| "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED1.TGR10", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8D", |
| "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED1.TGR8", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8D", |
| "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED1.TGR9", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8E", |
| "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8E", |
| "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8E", |
| "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR2", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8E", |
| "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR3", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", |
| "UMask": "0x8", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8E", |
| "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR4", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", |
| "UMask": "0x10", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8E", |
| "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR5", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", |
| "UMask": "0x20", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8E", |
| "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR6", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", |
| "UMask": "0x40", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8E", |
| "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR7", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", |
| "UMask": "0x80", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8F", |
| "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY1.TGR10", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8F", |
| "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY1.TGR8", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8F", |
| "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY1.TGR9", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "M2M to iMC Bypass : Not Taken", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x22", |
| "EventName": "UNC_M2M_BYPASS_M2M_EGRESS.NOT_TAKEN", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "M2M to iMC Bypass : Taken", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x22", |
| "EventName": "UNC_M2M_BYPASS_M2M_EGRESS.TAKEN", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "M2M to iMC Bypass : Not Taken", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x21", |
| "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.NOT_TAKEN", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "M2M to iMC Bypass : Taken", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x21", |
| "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.TAKEN", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Clockticks of the mesh to memory (M2M)", |
| "Counter": "0,1,2,3", |
| "EventName": "UNC_M2M_CLOCKTICKS", |
| "PerPkg": "1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Clockticks", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xc0", |
| "EventName": "UNC_M2M_CMS_CLOCKTICKS", |
| "PerPkg": "1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Cycles when direct to core mode, which bypasses the CHA, was disabled", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x24", |
| "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_DIRSTATE", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_NOTFORKED", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x60", |
| "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_NOTFORKED", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Number of reads in which direct to core transaction was overridden", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x25", |
| "EventName": "UNC_M2M_DIRECT2CORE_TXN_OVERRIDE", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Distress signal asserted : DPT Local", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xAF", |
| "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_LOCAL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Distress signal asserted : DPT Local : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle triggered by this tile", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Distress signal asserted : DPT Remote", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xAF", |
| "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_NONLOCAL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Distress signal asserted : DPT Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle received by this tile", |
| "UMask": "0x8", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Distress signal asserted : DPT Stalled - IV", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xAF", |
| "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_STALL_IV", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Distress signal asserted : DPT Stalled - IV : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while regular IVs were received, causing DPT to be stalled", |
| "UMask": "0x40", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Distress signal asserted : DPT Stalled - No Credit", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xAF", |
| "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_STALL_NOCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Distress signal asserted : DPT Stalled - No Credit : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while credit not available causing DPT to be stalled", |
| "UMask": "0x80", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Distress signal asserted : Horizontal", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xAF", |
| "EventName": "UNC_M2M_DISTRESS_ASSERTED.HORZ", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Distress signal asserted : Horizontal : Counts the number of cycles either the local or incoming distress signals are asserted. : If TGR egress is full, then agents will throttle outgoing AD IDI transactions", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Distress signal asserted : Vertical", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xAF", |
| "EventName": "UNC_M2M_DISTRESS_ASSERTED.VERT", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Distress signal asserted : Vertical : Counts the number of cycles either the local or incoming distress signals are asserted. : If IRQ egress is full, then agents will throttle outgoing AD IDI transactions", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Egress Blocking due to Ordering requirements : Down", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xBA", |
| "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_DN", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Egress Blocking due to Ordering requirements : Down : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Egress Blocking due to Ordering requirements : Up", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xBA", |
| "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_UP", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Egress Blocking due to Ordering requirements : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Horizontal AD Ring In Use : Left and Even", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xB6", |
| "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_EVEN", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Horizontal AD Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Horizontal AD Ring In Use : Left and Odd", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xB6", |
| "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_ODD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Horizontal AD Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Horizontal AD Ring In Use : Right and Even", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xB6", |
| "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_EVEN", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Horizontal AD Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Horizontal AD Ring In Use : Right and Odd", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xB6", |
| "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_ODD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Horizontal AD Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x8", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Horizontal AK Ring In Use : Left and Even", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xBB", |
| "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.LEFT_EVEN", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xBB", |
| "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.LEFT_ODD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Horizontal AK Ring In Use : Right and Even", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xBB", |
| "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.RIGHT_EVEN", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xBB", |
| "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.RIGHT_ODD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x8", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Horizontal AK Ring In Use : Left and Even", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xB7", |
| "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_EVEN", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xB7", |
| "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_ODD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Horizontal AK Ring In Use : Right and Even", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xB7", |
| "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_EVEN", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xB7", |
| "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_ODD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x8", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Horizontal BL Ring in Use : Left and Even", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xB8", |
| "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_EVEN", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Horizontal BL Ring in Use : Left and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Horizontal BL Ring in Use : Left and Odd", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xB8", |
| "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_ODD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Horizontal BL Ring in Use : Left and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Horizontal BL Ring in Use : Right and Even", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xB8", |
| "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_EVEN", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Horizontal BL Ring in Use : Right and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Horizontal BL Ring in Use : Right and Odd", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xB8", |
| "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_ODD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Horizontal BL Ring in Use : Right and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x8", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Horizontal IV Ring in Use : Left", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xB9", |
| "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.LEFT", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Horizontal IV Ring in Use : Left : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Horizontal IV Ring in Use : Right", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xB9", |
| "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.RIGHT", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Horizontal IV Ring in Use : Right : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "M2M Reads Issued to iMC : All, regardless of priority. - All Channels", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x37", |
| "EventName": "UNC_M2M_IMC_READS.ALL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x704", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "M2M Reads Issued to iMC : All, regardless of priority. - Ch0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x37", |
| "EventName": "UNC_M2M_IMC_READS.CH0_ALL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x104", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "M2M Reads Issued to iMC : From TGR - Ch0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x37", |
| "EventName": "UNC_M2M_IMC_READS.CH0_FROM_TGR", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x140", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "M2M Reads Issued to iMC : Critical Priority - Ch0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x37", |
| "EventName": "UNC_M2M_IMC_READS.CH0_ISOCH", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x102", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "M2M Reads Issued to iMC : Normal Priority - Ch0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x37", |
| "EventName": "UNC_M2M_IMC_READS.CH0_NORMAL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x101", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "M2M Reads Issued to iMC : All, regardless of priority. - Ch1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x37", |
| "EventName": "UNC_M2M_IMC_READS.CH1_ALL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x204", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "M2M Reads Issued to iMC : From TGR - Ch1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x37", |
| "EventName": "UNC_M2M_IMC_READS.CH1_FROM_TGR", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x240", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "M2M Reads Issued to iMC : Critical Priority - Ch1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x37", |
| "EventName": "UNC_M2M_IMC_READS.CH1_ISOCH", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x202", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "M2M Reads Issued to iMC : Normal Priority - Ch1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x37", |
| "EventName": "UNC_M2M_IMC_READS.CH1_NORMAL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x201", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "M2M Reads Issued to iMC : From TGR - All Channels", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x37", |
| "EventName": "UNC_M2M_IMC_READS.FROM_TGR", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x740", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "M2M Reads Issued to iMC : Critical Priority - All Channels", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x37", |
| "EventName": "UNC_M2M_IMC_READS.ISOCH", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x702", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "M2M Reads Issued to iMC : Normal Priority - All Channels", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x37", |
| "EventName": "UNC_M2M_IMC_READS.NORMAL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x701", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "M2M Writes Issued to iMC : All Writes - All Channels", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x38", |
| "EventName": "UNC_M2M_IMC_WRITES.ALL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1c10", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "M2M Writes Issued to iMC : All Writes - Ch0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x38", |
| "EventName": "UNC_M2M_IMC_WRITES.CH0_ALL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x410", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "M2M Writes Issued to iMC : From TGR - Ch0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x38", |
| "EventName": "UNC_M2M_IMC_WRITES.CH0_FROM_TGR", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "M2M Writes Issued to iMC : Full Line Non-ISOCH - Ch0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x38", |
| "EventName": "UNC_M2M_IMC_WRITES.CH0_FULL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x401", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "M2M Writes Issued to iMC : ISOCH Full Line - Ch0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x38", |
| "EventName": "UNC_M2M_IMC_WRITES.CH0_FULL_ISOCH", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x404", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive Miss - Ch0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x38", |
| "EventName": "UNC_M2M_IMC_WRITES.CH0_NI_MISS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "M2M Writes Issued to iMC : Partial Non-ISOCH - Ch0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x38", |
| "EventName": "UNC_M2M_IMC_WRITES.CH0_PARTIAL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x402", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "M2M Writes Issued to iMC : ISOCH Partial - Ch0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x38", |
| "EventName": "UNC_M2M_IMC_WRITES.CH0_PARTIAL_ISOCH", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x408", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "M2M Writes Issued to iMC : All Writes - Ch1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x38", |
| "EventName": "UNC_M2M_IMC_WRITES.CH1_ALL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x810", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "M2M Writes Issued to iMC : From TGR - Ch1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x38", |
| "EventName": "UNC_M2M_IMC_WRITES.CH1_FROM_TGR", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "M2M Writes Issued to iMC : Full Line Non-ISOCH - Ch1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x38", |
| "EventName": "UNC_M2M_IMC_WRITES.CH1_FULL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x801", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "M2M Writes Issued to iMC : ISOCH Full Line - Ch1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x38", |
| "EventName": "UNC_M2M_IMC_WRITES.CH1_FULL_ISOCH", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x804", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive Miss - Ch1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x38", |
| "EventName": "UNC_M2M_IMC_WRITES.CH1_NI_MISS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "M2M Writes Issued to iMC : Partial Non-ISOCH - Ch1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x38", |
| "EventName": "UNC_M2M_IMC_WRITES.CH1_PARTIAL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x802", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "M2M Writes Issued to iMC : ISOCH Partial - Ch1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x38", |
| "EventName": "UNC_M2M_IMC_WRITES.CH1_PARTIAL_ISOCH", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x808", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "M2M Writes Issued to iMC : From TGR - All Channels", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x38", |
| "EventName": "UNC_M2M_IMC_WRITES.FROM_TGR", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "M2M Writes Issued to iMC : Full Line Non-ISOCH - All Channels", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x38", |
| "EventName": "UNC_M2M_IMC_WRITES.FULL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1c01", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "M2M Writes Issued to iMC : ISOCH Full Line - All Channels", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x38", |
| "EventName": "UNC_M2M_IMC_WRITES.FULL_ISOCH", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1c04", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive Miss - All Channels", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x38", |
| "EventName": "UNC_M2M_IMC_WRITES.NI_MISS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "M2M Writes Issued to iMC : Partial Non-ISOCH - All Channels", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x38", |
| "EventName": "UNC_M2M_IMC_WRITES.PARTIAL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1c02", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "M2M Writes Issued to iMC : ISOCH Partial - All Channels", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x38", |
| "EventName": "UNC_M2M_IMC_WRITES.PARTIAL_ISOCH", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1c08", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Write Tracker Inserts", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x64", |
| "EventName": "UNC_M2M_MIRR_WRQ_INSERTS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Write Tracker Occupancy", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x65", |
| "EventName": "UNC_M2M_MIRR_WRQ_OCCUPANCY", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xE6", |
| "EventName": "UNC_M2M_MISC_EXTERNAL.MBE_INST0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xE6", |
| "EventName": "UNC_M2M_MISC_EXTERNAL.MBE_INST1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Number Packet Header Matches : MC Match", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x4C", |
| "EventName": "UNC_M2M_PKT_MATCH.MC", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Number Packet Header Matches : Mesh Match", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x4C", |
| "EventName": "UNC_M2M_PKT_MATCH.MESH", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "UNC_M2M_PREFCAM_CIS_DROPS", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x73", |
| "EventName": "UNC_M2M_PREFCAM_CIS_DROPS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Prefetch CAM Cycles Full : All Channels", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x6B", |
| "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.ALLCH", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x7", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Prefetch CAM Cycles Full : Channel 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x6B", |
| "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.CH0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Prefetch CAM Cycles Full : Channel 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x6B", |
| "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.CH1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Prefetch CAM Cycles Not Empty : All Channels", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x6C", |
| "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.ALLCH", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x7", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Prefetch CAM Cycles Not Empty : Channel 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x6C", |
| "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.CH0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Prefetch CAM Cycles Not Empty : Channel 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x6C", |
| "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.CH1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Prefetch CAM Deallocs", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x6E", |
| "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_HITA0_INVAL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Prefetch CAM Deallocs", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x6E", |
| "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_HITA1_INVAL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Prefetch CAM Deallocs", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x6E", |
| "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_MISS_INVAL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Prefetch CAM Deallocs", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x6E", |
| "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_RSP_PDRESET", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x8", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Prefetch CAM Deallocs", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x6E", |
| "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_HITA0_INVAL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x10", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Prefetch CAM Deallocs", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x6E", |
| "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_HITA1_INVAL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x20", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Prefetch CAM Deallocs", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x6E", |
| "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_MISS_INVAL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x40", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Prefetch CAM Deallocs", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x6E", |
| "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_RSP_PDRESET", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x80", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Data Prefetches Dropped : XPT - Ch 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x6F", |
| "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH0_XPT", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Data Prefetches Dropped : XPT - Ch 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x6F", |
| "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH1_XPT", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Data Prefetches Dropped : XPT - All Channels", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x6f", |
| "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.XPT_ALLCH", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x15", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Demands Merged with CAMed Prefetches : XPT - Ch 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x74", |
| "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH0_XPT", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI- Ch 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x74", |
| "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH0_XPTUPI", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Demands Merged with CAMed Prefetches : XPT & UPI - Ch 0", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Demands Merged with CAMed Prefetches : XPT - Ch 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x74", |
| "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH1_XPT", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI - Ch 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x74", |
| "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH1_XPTUPI", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Demands Merged with CAMed Prefetches : XPT & UPI- Ch 1", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI- Ch 2", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x74", |
| "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH2_XPTUPI", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Demands Merged with CAMed Prefetches : XPT & UPI - Ch 2", |
| "UMask": "0x10", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI- All Channels", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x74", |
| "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.XPTUPI_ALLCH", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Demands Merged with CAMed Prefetches : XPT & UPI - All Channels", |
| "UMask": "0x15", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Demands Merged with CAMed Prefetches : XPT - All Channels", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x74", |
| "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.XPT_ALLCH", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x15", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT - Ch 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x75", |
| "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH0_XPT", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - Ch 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x75", |
| "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH0_XPTUPI", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI- Ch 0", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT - Ch 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x75", |
| "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH1_XPT", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - Ch 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x75", |
| "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH1_XPTUPI", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI- Ch 1", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - Ch 2", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x75", |
| "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH2_XPTUPI", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x10", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - All Channels", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x75", |
| "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.XPTUPI_ALLCH", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x15", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT - All Channels", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x75", |
| "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.XPT_ALLCH", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x15", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x70", |
| "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.ERRORBLK_RxC", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x10", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x70", |
| "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.NOT_PF_SAD_REGION", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x70", |
| "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_AD_CRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x20", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x70", |
| "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_CAM_FULL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x40", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x70", |
| "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_CAM_HIT", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x70", |
| "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_SECURE_DROP", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x70", |
| "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.RPQ_PROXY", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x70", |
| "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.STOP_B2B", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x8", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x70", |
| "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.WPQ_PROXY", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x80", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x70", |
| "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.XPT_THRESH", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x71", |
| "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.ERRORBLK_RxC", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x10", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x71", |
| "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.NOT_PF_SAD_REGION", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x71", |
| "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_AD_CRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x20", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x71", |
| "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_CAM_FULL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x40", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x71", |
| "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_CAM_HIT", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x71", |
| "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_SECURE_DROP", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x71", |
| "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.RPQ_PROXY", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x71", |
| "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.STOP_B2B", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x8", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x71", |
| "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.WPQ_PROXY", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x80", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x71", |
| "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.XPT_THRESH", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x6D", |
| "EventName": "UNC_M2M_PREFCAM_INSERTS.CH0_XPT", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x6D", |
| "EventName": "UNC_M2M_PREFCAM_INSERTS.CH1_XPT", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Prefetch CAM Inserts : XPT - All Channels", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x6D", |
| "EventName": "UNC_M2M_PREFCAM_INSERTS.XPT_ALLCH", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x15", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Prefetch CAM Occupancy : All Channels", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x6A", |
| "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.ALLCH", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x7", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Prefetch CAM Occupancy : Channel 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x6A", |
| "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.CH0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Prefetch CAM Occupancy : Channel 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x6A", |
| "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.CH1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": ": All Channels", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x76", |
| "EventName": "UNC_M2M_PREFCAM_RESP_MISS.ALLCH", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x7", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": ": Channel 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x76", |
| "EventName": "UNC_M2M_PREFCAM_RESP_MISS.CH0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": ": Channel 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x76", |
| "EventName": "UNC_M2M_PREFCAM_RESP_MISS.CH1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "UNC_M2M_PREFCAM_RxC_CYCLES_NE", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x79", |
| "EventName": "UNC_M2M_PREFCAM_RxC_CYCLES_NE", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.1LM_POSTED", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x7A", |
| "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.1LM_POSTED", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.CIS", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x7A", |
| "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.CIS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x8", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.SQUASHED", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x7A", |
| "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.SQUASHED", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "UNC_M2M_PREFCAM_RxC_INSERTS", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x78", |
| "EventName": "UNC_M2M_PREFCAM_RxC_INSERTS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "UNC_M2M_PREFCAM_RxC_OCCUPANCY", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x77", |
| "EventName": "UNC_M2M_PREFCAM_RxC_OCCUPANCY", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Messages that bounced on the Horizontal Ring. : AD", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xAC", |
| "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Messages that bounced on the Horizontal Ring. : AD : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Messages that bounced on the Horizontal Ring. : AK", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xAC", |
| "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AK", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Messages that bounced on the Horizontal Ring. : AK : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Messages that bounced on the Horizontal Ring. : BL", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xAC", |
| "EventName": "UNC_M2M_RING_BOUNCES_HORZ.BL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Messages that bounced on the Horizontal Ring. : BL : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Messages that bounced on the Horizontal Ring. : IV", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xAC", |
| "EventName": "UNC_M2M_RING_BOUNCES_HORZ.IV", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Messages that bounced on the Horizontal Ring. : IV : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", |
| "UMask": "0x8", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Messages that bounced on the Vertical Ring. : AD", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xAA", |
| "EventName": "UNC_M2M_RING_BOUNCES_VERT.AD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Messages that bounced on the Vertical Ring. : AD : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xAA", |
| "EventName": "UNC_M2M_RING_BOUNCES_VERT.AK", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Messages that bounced on the Vertical Ring.", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xAA", |
| "EventName": "UNC_M2M_RING_BOUNCES_VERT.AKC", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Messages that bounced on the Vertical Ring. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", |
| "UMask": "0x10", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xAA", |
| "EventName": "UNC_M2M_RING_BOUNCES_VERT.BL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache.", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xAA", |
| "EventName": "UNC_M2M_RING_BOUNCES_VERT.IV", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", |
| "UMask": "0x8", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Sink Starvation on Horizontal Ring : AD", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xAD", |
| "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Sink Starvation on Horizontal Ring : AK", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xAD", |
| "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xAD", |
| "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK_AG1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x20", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Sink Starvation on Horizontal Ring : BL", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xAD", |
| "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.BL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Sink Starvation on Horizontal Ring : IV", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xAD", |
| "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.IV", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x8", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Sink Starvation on Vertical Ring : AD", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xAB", |
| "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Sink Starvation on Vertical Ring : Acknowledgements to core", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xAB", |
| "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AK", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Sink Starvation on Vertical Ring", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xAB", |
| "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AKC", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x10", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Sink Starvation on Vertical Ring : Data Responses to core", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xAB", |
| "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.BL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of processor's cache.", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xAB", |
| "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.IV", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x8", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Source Throttle", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xae", |
| "EventName": "UNC_M2M_RING_SRC_THRTL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular : Channel 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x43", |
| "EventName": "UNC_M2M_RPQ_NO_REG_CRD.CH0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular : Channel 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x43", |
| "EventName": "UNC_M2M_RPQ_NO_REG_CRD.CH1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special : Channel 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x44", |
| "EventName": "UNC_M2M_RPQ_NO_SPEC_CRD.CH0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special : Channel 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x44", |
| "EventName": "UNC_M2M_RPQ_NO_SPEC_CRD.CH1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "AD Ingress (from CMS) Full", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x04", |
| "EventName": "UNC_M2M_RxC_AD_CYCLES_FULL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "AD Ingress (from CMS) Not Empty", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x03", |
| "EventName": "UNC_M2M_RxC_AD_CYCLES_NE", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "AD Ingress (from CMS) Allocations", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x01", |
| "EventName": "UNC_M2M_RxC_AD_INSERTS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "AD Ingress (from CMS) Occupancy", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x02", |
| "EventName": "UNC_M2M_RxC_AD_OCCUPANCY", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "AD Ingress (from CMS) Occupancy - Prefetches", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x77", |
| "EventName": "UNC_M2M_RxC_AD_PREF_OCCUPANCY", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "AK Egress (to CMS) Allocations", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x5C", |
| "EventName": "UNC_M2M_RxC_AK_WR_CMP", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "BL Ingress (from CMS) Full", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x08", |
| "EventName": "UNC_M2M_RxC_BL_CYCLES_FULL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "BL Ingress (from CMS) Not Empty", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x07", |
| "EventName": "UNC_M2M_RxC_BL_CYCLES_NE", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "BL Ingress (from CMS) Allocations", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x05", |
| "EventName": "UNC_M2M_RxC_BL_INSERTS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "BL Ingress (from CMS) Occupancy", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x06", |
| "EventName": "UNC_M2M_RxC_BL_OCCUPANCY", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Transgress Injection Starvation : AD - All", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xE5", |
| "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_ALL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited", |
| "UMask": "0x11", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Transgress Injection Starvation : AD - Credited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xE5", |
| "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_CRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", |
| "UMask": "0x10", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Transgress Injection Starvation : AD - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xE5", |
| "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Transgress Injection Starvation : BL - All", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xE5", |
| "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_ALL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited", |
| "UMask": "0x44", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Transgress Injection Starvation : BL - Credited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xE5", |
| "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_CRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", |
| "UMask": "0x40", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Transgress Injection Starvation : BL - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xE5", |
| "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Transgress Ingress Bypass : AD - All", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xE2", |
| "EventName": "UNC_M2M_RxR_BYPASS.AD_ALL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Ingress Bypass : AD - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited", |
| "UMask": "0x11", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Transgress Ingress Bypass : AD - Credited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xE2", |
| "EventName": "UNC_M2M_RxR_BYPASS.AD_CRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Ingress Bypass : AD - Credited : Number of packets bypassing the CMS Ingress", |
| "UMask": "0x10", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Transgress Ingress Bypass : AD - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xE2", |
| "EventName": "UNC_M2M_RxR_BYPASS.AD_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Ingress Bypass : AD - Uncredited : Number of packets bypassing the CMS Ingress", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Transgress Ingress Bypass : AK", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xE2", |
| "EventName": "UNC_M2M_RxR_BYPASS.AK", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Ingress Bypass : AK : Number of packets bypassing the CMS Ingress", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xE2", |
| "EventName": "UNC_M2M_RxR_BYPASS.AKC_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Ingress Bypass : AKC - Uncredited : Number of packets bypassing the CMS Ingress", |
| "UMask": "0x80", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Transgress Ingress Bypass : BL - All", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xE2", |
| "EventName": "UNC_M2M_RxR_BYPASS.BL_ALL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Ingress Bypass : BL - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited", |
| "UMask": "0x44", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Transgress Ingress Bypass : BL - Credited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xE2", |
| "EventName": "UNC_M2M_RxR_BYPASS.BL_CRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Ingress Bypass : BL - Credited : Number of packets bypassing the CMS Ingress", |
| "UMask": "0x40", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xE2", |
| "EventName": "UNC_M2M_RxR_BYPASS.BL_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Ingress Bypass : BL - Uncredited : Number of packets bypassing the CMS Ingress", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Transgress Ingress Bypass : IV", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xE2", |
| "EventName": "UNC_M2M_RxR_BYPASS.IV", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Ingress Bypass : IV : Number of packets bypassing the CMS Ingress", |
| "UMask": "0x8", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Transgress Injection Starvation : AD - All", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xE3", |
| "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_ALL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited", |
| "UMask": "0x11", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Transgress Injection Starvation : AD - Credited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xE3", |
| "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_CRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", |
| "UMask": "0x10", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Transgress Injection Starvation : AD - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xE3", |
| "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Transgress Injection Starvation : AK", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xE3", |
| "EventName": "UNC_M2M_RxR_CRD_STARVED.AK", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Injection Starvation : AK : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Transgress Injection Starvation : BL - All", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xE3", |
| "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_ALL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited", |
| "UMask": "0x44", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Transgress Injection Starvation : BL - Credited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xE3", |
| "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_CRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", |
| "UMask": "0x40", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Transgress Injection Starvation : BL - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xE3", |
| "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Transgress Injection Starvation : IFV - Credited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xE3", |
| "EventName": "UNC_M2M_RxR_CRD_STARVED.IFV", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Injection Starvation : IFV - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", |
| "UMask": "0x80", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Transgress Injection Starvation : IV", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xE3", |
| "EventName": "UNC_M2M_RxR_CRD_STARVED.IV", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Injection Starvation : IV : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", |
| "UMask": "0x8", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Transgress Injection Starvation", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xe4", |
| "EventName": "UNC_M2M_RxR_CRD_STARVED_1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Injection Starvation : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Transgress Ingress Allocations : AD - All", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xE1", |
| "EventName": "UNC_M2M_RxR_INSERTS.AD_ALL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Ingress Allocations : AD - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited", |
| "UMask": "0x11", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Transgress Ingress Allocations : AD - Credited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xE1", |
| "EventName": "UNC_M2M_RxR_INSERTS.AD_CRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Ingress Allocations : AD - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", |
| "UMask": "0x10", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Transgress Ingress Allocations : AD - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xE1", |
| "EventName": "UNC_M2M_RxR_INSERTS.AD_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Ingress Allocations : AD - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Transgress Ingress Allocations : AK", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xE1", |
| "EventName": "UNC_M2M_RxR_INSERTS.AK", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Ingress Allocations : AK : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Transgress Ingress Allocations : AKC - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xE1", |
| "EventName": "UNC_M2M_RxR_INSERTS.AKC_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Ingress Allocations : AKC - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", |
| "UMask": "0x80", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Transgress Ingress Allocations : BL - All", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xE1", |
| "EventName": "UNC_M2M_RxR_INSERTS.BL_ALL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Ingress Allocations : BL - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited", |
| "UMask": "0x44", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Transgress Ingress Allocations : BL - Credited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xE1", |
| "EventName": "UNC_M2M_RxR_INSERTS.BL_CRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Ingress Allocations : BL - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", |
| "UMask": "0x40", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Transgress Ingress Allocations : BL - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xE1", |
| "EventName": "UNC_M2M_RxR_INSERTS.BL_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Ingress Allocations : BL - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Transgress Ingress Allocations : IV", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xE1", |
| "EventName": "UNC_M2M_RxR_INSERTS.IV", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Ingress Allocations : IV : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", |
| "UMask": "0x8", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Transgress Ingress Occupancy : AD - All", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xE0", |
| "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_ALL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Ingress Occupancy : AD - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited", |
| "UMask": "0x11", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Transgress Ingress Occupancy : AD - Credited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xE0", |
| "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_CRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Ingress Occupancy : AD - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", |
| "UMask": "0x10", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Transgress Ingress Occupancy : AD - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xE0", |
| "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Ingress Occupancy : AD - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Transgress Ingress Occupancy : AK", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xE0", |
| "EventName": "UNC_M2M_RxR_OCCUPANCY.AK", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Ingress Occupancy : AK : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xE0", |
| "EventName": "UNC_M2M_RxR_OCCUPANCY.AKC_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Ingress Occupancy : AKC - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", |
| "UMask": "0x80", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Transgress Ingress Occupancy : BL - All", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xE0", |
| "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_ALL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Ingress Occupancy : BL - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited", |
| "UMask": "0x44", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Transgress Ingress Occupancy : BL - Credited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xE0", |
| "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_CRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Ingress Occupancy : BL - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", |
| "UMask": "0x20", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xE0", |
| "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Ingress Occupancy : BL - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Transgress Ingress Occupancy : IV", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xE0", |
| "EventName": "UNC_M2M_RxR_OCCUPANCY.IV", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Ingress Occupancy : IV : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", |
| "UMask": "0x8", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xD0", |
| "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xD0", |
| "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xD0", |
| "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR2", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xD0", |
| "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR3", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x8", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xD0", |
| "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR4", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x10", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xD0", |
| "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR5", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x20", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xD0", |
| "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR6", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x40", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xD0", |
| "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR7", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x80", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xD2", |
| "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xD2", |
| "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xD2", |
| "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR2", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xD2", |
| "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR3", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x8", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xD2", |
| "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR4", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x10", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xD2", |
| "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR5", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x20", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xD2", |
| "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR6", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x40", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xD2", |
| "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR7", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x80", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xD4", |
| "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xD4", |
| "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xD4", |
| "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR2", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xD4", |
| "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR3", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x8", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xD4", |
| "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR4", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x10", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xD4", |
| "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR5", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x20", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xD4", |
| "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x40", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xD4", |
| "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x80", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xD6", |
| "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xD6", |
| "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xD6", |
| "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xD6", |
| "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x8", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xD6", |
| "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x10", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xD6", |
| "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x20", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xD6", |
| "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x40", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xD6", |
| "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x80", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xD1", |
| "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xD1", |
| "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xD1", |
| "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xD3", |
| "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xD3", |
| "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xD3", |
| "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xD5", |
| "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xD5", |
| "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xD5", |
| "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xD7", |
| "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xD7", |
| "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xD7", |
| "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Number AD Ingress Credits", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x41", |
| "EventName": "UNC_M2M_TGR_AD_CREDITS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Number BL Ingress Credits", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x42", |
| "EventName": "UNC_M2M_TGR_BL_CREDITS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Tracker Cycles Full : Channel 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x45", |
| "EventName": "UNC_M2M_TRACKER_FULL.CH0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Tracker Cycles Full : Channel 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x45", |
| "EventName": "UNC_M2M_TRACKER_FULL.CH1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Tracker Inserts : Channel 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x49", |
| "EventName": "UNC_M2M_TRACKER_INSERTS.CH0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Tracker Inserts : Channel 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x49", |
| "EventName": "UNC_M2M_TRACKER_INSERTS.CH1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Tracker Cycles Not Empty : Channel 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x46", |
| "EventName": "UNC_M2M_TRACKER_NE.CH0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Tracker Cycles Not Empty : Channel 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x46", |
| "EventName": "UNC_M2M_TRACKER_NE.CH1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Tracker Occupancy : Channel 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x47", |
| "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Tracker Occupancy : Channel 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x47", |
| "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "AD Egress (to CMS) Credit Acquired", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x0d", |
| "EventName": "UNC_M2M_TxC_AD_CREDITS_ACQUIRED", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "AD Egress (to CMS) Credits Occupancy", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x0e", |
| "EventName": "UNC_M2M_TxC_AD_CREDIT_OCCUPANCY", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "AD Egress (to CMS) Full", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x0c", |
| "EventName": "UNC_M2M_TxC_AD_CYCLES_FULL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "AD Egress (to CMS) Not Empty", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x0b", |
| "EventName": "UNC_M2M_TxC_AD_CYCLES_NE", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "AD Egress (to CMS) Allocations", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x09", |
| "EventName": "UNC_M2M_TxC_AD_INSERTS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Cycles with No AD Egress (to CMS) Credits", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x0f", |
| "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_CYCLES", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Cycles Stalled with No AD Egress (to CMS) Credits", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x10", |
| "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_STALLED", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "AD Egress (to CMS) Occupancy", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x0A", |
| "EventName": "UNC_M2M_TxC_AD_OCCUPANCY", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Outbound Ring Transactions on AK : CRD Transactions to Cbo", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x39", |
| "EventName": "UNC_M2M_TxC_AK.CRD_CBO", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Outbound Ring Transactions on AK : NDR Transactions", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x39", |
| "EventName": "UNC_M2M_TxC_AK.NDR", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "AKC Credits", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x5F", |
| "EventName": "UNC_M2M_TxC_AKC_CREDITS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "AK Egress (to CMS) Credit Acquired : Common Mesh Stop - Near Side", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x1D", |
| "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "AK Egress (to CMS) Credit Acquired : Common Mesh Stop - Far Side", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x1D", |
| "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "AK Egress (to CMS) Full : All", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x14", |
| "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.ALL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x3", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "AK Egress (to CMS) Full : Common Mesh Stop - Near Side", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x14", |
| "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "AK Egress (to CMS) Full : Common Mesh Stop - Far Side", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x14", |
| "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "AK Egress (to CMS) Full", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x14", |
| "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x8", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "AK Egress (to CMS) Full", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x14", |
| "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x88", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "AK Egress (to CMS) Full", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x14", |
| "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x20", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "AK Egress (to CMS) Full", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x14", |
| "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0xa0", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "AK Egress (to CMS) Full", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x14", |
| "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x10", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "AK Egress (to CMS) Full", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x14", |
| "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x90", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "AK Egress (to CMS) Not Empty : All", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x13", |
| "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.ALL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x3", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "AK Egress (to CMS) Not Empty : Common Mesh Stop - Near Side", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x13", |
| "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "AK Egress (to CMS) Not Empty : Common Mesh Stop - Far Side", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x13", |
| "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "AK Egress (to CMS) Not Empty", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x13", |
| "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.RDCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x8", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "AK Egress (to CMS) Not Empty", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x13", |
| "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCMP", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x20", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "AK Egress (to CMS) Not Empty", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x13", |
| "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x10", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "AK Egress (to CMS) Allocations : All", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x11", |
| "EventName": "UNC_M2M_TxC_AK_INSERTS.ALL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x3", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "AK Egress (to CMS) Allocations : Common Mesh Stop - Near Side", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x11", |
| "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "AK Egress (to CMS) Allocations : Common Mesh Stop - Far Side", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x11", |
| "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "AK Egress (to CMS) Allocations", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x11", |
| "EventName": "UNC_M2M_TxC_AK_INSERTS.PREF_RD_CAM_HIT", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x40", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "AK Egress (to CMS) Allocations", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x11", |
| "EventName": "UNC_M2M_TxC_AK_INSERTS.RDCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x8", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "AK Egress (to CMS) Allocations", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x11", |
| "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCMP", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x20", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "AK Egress (to CMS) Allocations", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x11", |
| "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x10", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Cycles with No AK Egress (to CMS) Credits : Common Mesh Stop - Near Side", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x1F", |
| "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Cycles with No AK Egress (to CMS) Credits : Common Mesh Stop - Far Side", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x1F", |
| "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Credits : Common Mesh Stop - Near Side", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x20", |
| "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Credits : Common Mesh Stop - Far Side", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x20", |
| "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "AK Egress (to CMS) Occupancy : All", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x12", |
| "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.ALL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x3", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "AK Egress (to CMS) Occupancy : Common Mesh Stop - Near Side", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x12", |
| "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "AK Egress (to CMS) Occupancy : Common Mesh Stop - Far Side", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x12", |
| "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "AK Egress (to CMS) Occupancy", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x12", |
| "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.RDCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x8", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "AK Egress (to CMS) Occupancy", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x12", |
| "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCMP", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x20", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "AK Egress (to CMS) Occupancy", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x12", |
| "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x10", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Outbound DRS Ring Transactions to Cache : Data to Cache", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x40", |
| "EventName": "UNC_M2M_TxC_BL.DRS_CACHE", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Outbound DRS Ring Transactions to Cache : Data to Core", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x40", |
| "EventName": "UNC_M2M_TxC_BL.DRS_CORE", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "BL Egress (to CMS) Credit Acquired : Common Mesh Stop - Near Side", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x19", |
| "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "BL Egress (to CMS) Credit Acquired : Common Mesh Stop - Far Side", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x19", |
| "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "BL Egress (to CMS) Full : All", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x18", |
| "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.ALL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x3", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "BL Egress (to CMS) Full : Common Mesh Stop - Near Side", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x18", |
| "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "BL Egress (to CMS) Full : Common Mesh Stop - Far Side", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x18", |
| "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "BL Egress (to CMS) Not Empty : All", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x17", |
| "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.ALL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x3", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "BL Egress (to CMS) Not Empty : Common Mesh Stop - Near Side", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x17", |
| "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "BL Egress (to CMS) Not Empty : Common Mesh Stop - Far Side", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x17", |
| "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "BL Egress (to CMS) Allocations : All", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x15", |
| "EventName": "UNC_M2M_TxC_BL_INSERTS.ALL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x3", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "BL Egress (to CMS) Allocations : Common Mesh Stop - Near Side", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x15", |
| "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "BL Egress (to CMS) Allocations : Common Mesh Stop - Far Side", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x15", |
| "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Cycles with No BL Egress (to CMS) Credits : Common Mesh Stop - Near Side", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x1B", |
| "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Cycles with No BL Egress (to CMS) Credits : Common Mesh Stop - Far Side", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x1B", |
| "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Credits : Common Mesh Stop - Near Side", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x1C", |
| "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Credits : Common Mesh Stop - Far Side", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x1C", |
| "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal ADS Used : AD - All", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xA6", |
| "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_ALL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal ADS Used : AD - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited", |
| "UMask": "0x11", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal ADS Used : AD - Credited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xA6", |
| "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_CRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal ADS Used : AD - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", |
| "UMask": "0x10", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xA6", |
| "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal ADS Used : AD - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal ADS Used : BL - All", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xA6", |
| "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_ALL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal ADS Used : BL - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited", |
| "UMask": "0x44", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal ADS Used : BL - Credited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xA6", |
| "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_CRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal ADS Used : BL - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", |
| "UMask": "0x40", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xA6", |
| "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal ADS Used : BL - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Bypass Used : AD - All", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xA7", |
| "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_ALL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Bypass Used : AD - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited", |
| "UMask": "0x11", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xA7", |
| "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_CRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Bypass Used : AD - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", |
| "UMask": "0x10", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Bypass Used : AD - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xA7", |
| "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Bypass Used : AD - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Bypass Used : AK", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xA7", |
| "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AK", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Bypass Used : AK : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xA7", |
| "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AKC_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Bypass Used : AKC - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", |
| "UMask": "0x80", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Bypass Used : BL - All", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xA7", |
| "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_ALL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Bypass Used : BL - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited", |
| "UMask": "0x44", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xA7", |
| "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_CRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Bypass Used : BL - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", |
| "UMask": "0x40", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xA7", |
| "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Bypass Used : BL - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Bypass Used : IV", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xA7", |
| "EventName": "UNC_M2M_TxR_HORZ_BYPASS.IV", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Bypass Used : IV : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", |
| "UMask": "0x8", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xA2", |
| "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_ALL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", |
| "UMask": "0x11", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xA2", |
| "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_CRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", |
| "UMask": "0x10", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xA2", |
| "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AK", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xA2", |
| "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AK", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AK : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xA2", |
| "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AKC_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", |
| "UMask": "0x80", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xA2", |
| "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_ALL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", |
| "UMask": "0x44", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xA2", |
| "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_CRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", |
| "UMask": "0x40", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xA2", |
| "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : IV", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xA2", |
| "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.IV", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : IV : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", |
| "UMask": "0x8", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xA3", |
| "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_ALL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", |
| "UMask": "0x11", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xA3", |
| "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_CRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", |
| "UMask": "0x10", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xA3", |
| "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xA3", |
| "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AK", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xA3", |
| "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AKC_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", |
| "UMask": "0x80", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xA3", |
| "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_ALL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", |
| "UMask": "0x44", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xA3", |
| "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_CRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", |
| "UMask": "0x40", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xA3", |
| "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xA3", |
| "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.IV", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", |
| "UMask": "0x8", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Egress Inserts : AD - All", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xA1", |
| "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_ALL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Egress Inserts : AD - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", |
| "UMask": "0x11", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xA1", |
| "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_CRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Egress Inserts : AD - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", |
| "UMask": "0x10", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Egress Inserts : AD - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xA1", |
| "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Egress Inserts : AD - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Egress Inserts : AK", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xA1", |
| "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AK", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Egress Inserts : AK : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xA1", |
| "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AKC_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", |
| "UMask": "0x80", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Egress Inserts : BL - All", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xA1", |
| "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_ALL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Egress Inserts : BL - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", |
| "UMask": "0x44", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xA1", |
| "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_CRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Egress Inserts : BL - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", |
| "UMask": "0x40", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xA1", |
| "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Egress Inserts : BL - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Egress Inserts : IV", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xA1", |
| "EventName": "UNC_M2M_TxR_HORZ_INSERTS.IV", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Egress Inserts : IV : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", |
| "UMask": "0x8", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Egress NACKs : AD - All", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xA4", |
| "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_ALL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Egress NACKs : AD - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited", |
| "UMask": "0x11", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xA4", |
| "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_CRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Egress NACKs : AD - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", |
| "UMask": "0x10", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Egress NACKs : AD - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xA4", |
| "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Egress NACKs : AD - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Egress NACKs : AK", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xA4", |
| "EventName": "UNC_M2M_TxR_HORZ_NACK.AK", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Egress NACKs : AK : Counts number of Egress packets NACK'ed on to the Horizontal Ring", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xA4", |
| "EventName": "UNC_M2M_TxR_HORZ_NACK.AKC_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", |
| "UMask": "0x80", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Egress NACKs : BL - All", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xA4", |
| "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_ALL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Egress NACKs : BL - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited", |
| "UMask": "0x44", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xA4", |
| "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_CRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Egress NACKs : BL - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", |
| "UMask": "0x40", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xA4", |
| "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Egress NACKs : BL - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Egress NACKs : IV", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xA4", |
| "EventName": "UNC_M2M_TxR_HORZ_NACK.IV", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Horizontal Ring", |
| "UMask": "0x8", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xA0", |
| "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_ALL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Egress Occupancy : AD - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", |
| "UMask": "0x11", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xA0", |
| "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_CRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", |
| "UMask": "0x10", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xA0", |
| "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Egress Occupancy : AK", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xA0", |
| "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AK", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Egress Occupancy : AK : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xA0", |
| "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AKC_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", |
| "UMask": "0x80", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xA0", |
| "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_ALL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Egress Occupancy : BL - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", |
| "UMask": "0x44", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Credited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xA0", |
| "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_CRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", |
| "UMask": "0x40", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xA0", |
| "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Egress Occupancy : IV", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xA0", |
| "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.IV", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Egress Occupancy : IV : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", |
| "UMask": "0x8", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - All", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xA5", |
| "EventName": "UNC_M2M_TxR_HORZ_STARVED.AD_ALL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xA5", |
| "EventName": "UNC_M2M_TxR_HORZ_STARVED.AD_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Egress Injection Starvation : AK", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xA5", |
| "EventName": "UNC_M2M_TxR_HORZ_STARVED.AK", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Egress Injection Starvation : AK : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xA5", |
| "EventName": "UNC_M2M_TxR_HORZ_STARVED.AKC_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", |
| "UMask": "0x80", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - All", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xA5", |
| "EventName": "UNC_M2M_TxR_HORZ_STARVED.BL_ALL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xA5", |
| "EventName": "UNC_M2M_TxR_HORZ_STARVED.BL_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Egress Injection Starvation : IV", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xA5", |
| "EventName": "UNC_M2M_TxR_HORZ_STARVED.IV", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", |
| "UMask": "0x8", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x9C", |
| "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x9C", |
| "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", |
| "UMask": "0x10", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x9C", |
| "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x9C", |
| "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", |
| "UMask": "0x40", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x9D", |
| "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x9D", |
| "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", |
| "UMask": "0x10", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x9D", |
| "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vertical ADS Used : AK - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x9D", |
| "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vertical ADS Used : AK - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", |
| "UMask": "0x20", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x9D", |
| "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x9D", |
| "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", |
| "UMask": "0x40", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x9D", |
| "EventName": "UNC_M2M_TxR_VERT_BYPASS.IV_AG1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vertical ADS Used : IV - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", |
| "UMask": "0x8", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x9E", |
| "EventName": "UNC_M2M_TxR_VERT_BYPASS_1.AKC_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x9E", |
| "EventName": "UNC_M2M_TxR_VERT_BYPASS_1.AKC_AG1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x94", |
| "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AD_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x94", |
| "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AD_AG1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", |
| "UMask": "0x10", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x94", |
| "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AK_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x94", |
| "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AK_AG1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", |
| "UMask": "0x20", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x94", |
| "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.BL_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x94", |
| "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.BL_AG1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", |
| "UMask": "0x40", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x94", |
| "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.IV_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", |
| "UMask": "0x8", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x95", |
| "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL1.AKC_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x95", |
| "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL1.AKC_AG1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x96", |
| "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AD_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x96", |
| "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AD_AG1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", |
| "UMask": "0x10", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x96", |
| "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AK_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x96", |
| "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AK_AG1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", |
| "UMask": "0x20", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x96", |
| "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.BL_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x96", |
| "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.BL_AG1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", |
| "UMask": "0x40", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x96", |
| "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.IV_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", |
| "UMask": "0x8", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x97", |
| "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE1.AKC_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x97", |
| "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE1.AKC_AG1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x92", |
| "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AD_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x92", |
| "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AD_AG1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", |
| "UMask": "0x10", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x92", |
| "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AK_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x92", |
| "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AK_AG1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", |
| "UMask": "0x20", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x92", |
| "EventName": "UNC_M2M_TxR_VERT_INSERTS0.BL_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x92", |
| "EventName": "UNC_M2M_TxR_VERT_INSERTS0.BL_AG1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", |
| "UMask": "0x40", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x92", |
| "EventName": "UNC_M2M_TxR_VERT_INSERTS0.IV_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vert Egress Allocations : IV - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", |
| "UMask": "0x8", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x93", |
| "EventName": "UNC_M2M_TxR_VERT_INSERTS1.AKC_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x93", |
| "EventName": "UNC_M2M_TxR_VERT_INSERTS1.AKC_AG1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x98", |
| "EventName": "UNC_M2M_TxR_VERT_NACK0.AD_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x98", |
| "EventName": "UNC_M2M_TxR_VERT_NACK0.AD_AG1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring", |
| "UMask": "0x10", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x98", |
| "EventName": "UNC_M2M_TxR_VERT_NACK0.AK_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x98", |
| "EventName": "UNC_M2M_TxR_VERT_NACK0.AK_AG1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring", |
| "UMask": "0x20", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x98", |
| "EventName": "UNC_M2M_TxR_VERT_NACK0.BL_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x98", |
| "EventName": "UNC_M2M_TxR_VERT_NACK0.BL_AG1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring", |
| "UMask": "0x40", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Vertical Egress NACKs : IV", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x98", |
| "EventName": "UNC_M2M_TxR_VERT_NACK0.IV_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vertical Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Vertical Ring", |
| "UMask": "0x8", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x99", |
| "EventName": "UNC_M2M_TxR_VERT_NACK1.AKC_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x99", |
| "EventName": "UNC_M2M_TxR_VERT_NACK1.AKC_AG1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x90", |
| "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AD_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x90", |
| "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AD_AG1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", |
| "UMask": "0x10", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x90", |
| "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AK_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x90", |
| "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AK_AG1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", |
| "UMask": "0x20", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x90", |
| "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.BL_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x90", |
| "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.BL_AG1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", |
| "UMask": "0x40", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x90", |
| "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.IV_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vert Egress Occupancy : IV - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", |
| "UMask": "0x8", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x91", |
| "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY1.AKC_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x91", |
| "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY1.AKC_AG1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x9A", |
| "EventName": "UNC_M2M_TxR_VERT_STARVED0.AD_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x9A", |
| "EventName": "UNC_M2M_TxR_VERT_STARVED0.AD_AG1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", |
| "UMask": "0x10", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x9A", |
| "EventName": "UNC_M2M_TxR_VERT_STARVED0.AK_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x9A", |
| "EventName": "UNC_M2M_TxR_VERT_STARVED0.AK_AG1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", |
| "UMask": "0x20", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x9A", |
| "EventName": "UNC_M2M_TxR_VERT_STARVED0.BL_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x9A", |
| "EventName": "UNC_M2M_TxR_VERT_STARVED0.BL_AG1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", |
| "UMask": "0x40", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Vertical Egress Injection Starvation : IV", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x9A", |
| "EventName": "UNC_M2M_TxR_VERT_STARVED0.IV_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vertical Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", |
| "UMask": "0x8", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x9B", |
| "EventName": "UNC_M2M_TxR_VERT_STARVED1.AKC_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x9B", |
| "EventName": "UNC_M2M_TxR_VERT_STARVED1.AKC_AG1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x9B", |
| "EventName": "UNC_M2M_TxR_VERT_STARVED1.TGC", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Vertical AD Ring In Use : Down and Even", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xB0", |
| "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_EVEN", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Vertical AD Ring In Use : Down and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Vertical AD Ring In Use : Down and Odd", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xB0", |
| "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_ODD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Vertical AD Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x8", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Vertical AD Ring In Use : Up and Even", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xB0", |
| "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_EVEN", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Vertical AD Ring In Use : Up and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Vertical AD Ring In Use : Up and Odd", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xB0", |
| "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_ODD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Vertical AD Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Vertical AKC Ring In Use : Down and Even", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xB4", |
| "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.DN_EVEN", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Vertical AKC Ring In Use : Down and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Vertical AKC Ring In Use : Down and Odd", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xB4", |
| "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.DN_ODD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Vertical AKC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x8", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Vertical AKC Ring In Use : Up and Even", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xB4", |
| "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.UP_EVEN", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Vertical AKC Ring In Use : Up and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Vertical AKC Ring In Use : Up and Odd", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xB4", |
| "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.UP_ODD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Vertical AKC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Vertical AK Ring In Use : Down and Even", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xB1", |
| "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_EVEN", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Vertical AK Ring In Use : Down and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Vertical AK Ring In Use : Down and Odd", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xB1", |
| "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_ODD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Vertical AK Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x8", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Vertical AK Ring In Use : Up and Even", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xB1", |
| "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_EVEN", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Vertical AK Ring In Use : Up and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Vertical AK Ring In Use : Up and Odd", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xB1", |
| "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_ODD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Vertical AK Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Vertical BL Ring in Use : Down and Even", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xB2", |
| "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_EVEN", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Vertical BL Ring in Use : Down and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Vertical BL Ring in Use : Down and Odd", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xB2", |
| "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_ODD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Vertical BL Ring in Use : Down and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x8", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Vertical BL Ring in Use : Up and Even", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xB2", |
| "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_EVEN", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Vertical BL Ring in Use : Up and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Vertical BL Ring in Use : Up and Odd", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xB2", |
| "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_ODD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Vertical BL Ring in Use : Up and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Vertical IV Ring in Use : Down", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xB3", |
| "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.DN", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Vertical IV Ring in Use : Down : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Vertical IV Ring in Use : Up", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xB3", |
| "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.UP", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Vertical IV Ring in Use : Up : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Vertical TGC Ring In Use : Down and Even", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xB5", |
| "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.DN_EVEN", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Vertical TGC Ring In Use : Down and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Vertical TGC Ring In Use : Down and Odd", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xB5", |
| "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.DN_ODD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Vertical TGC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x8", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Vertical TGC Ring In Use : Up and Even", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xB5", |
| "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.UP_EVEN", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Vertical TGC Ring In Use : Up and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Vertical TGC Ring In Use : Up and Odd", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xB5", |
| "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.UP_ODD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Vertical TGC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "WPQ Flush : Channel 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x58", |
| "EventName": "UNC_M2M_WPQ_FLUSH.CH0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "WPQ Flush : Channel 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x58", |
| "EventName": "UNC_M2M_WPQ_FLUSH.CH1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : Channel 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x4D", |
| "EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : Channel 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x4D", |
| "EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : Channel 2", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x4D", |
| "EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN2", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : Channel 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x4E", |
| "EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : Channel 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x4E", |
| "EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : Channel 2", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x4E", |
| "EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN2", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x4", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Write Tracker Cycles Full : Channel 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x4A", |
| "EventName": "UNC_M2M_WR_TRACKER_FULL.CH0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Write Tracker Cycles Full : Channel 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x4A", |
| "EventName": "UNC_M2M_WR_TRACKER_FULL.CH1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Write Tracker Cycles Full : Mirror", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x4A", |
| "EventName": "UNC_M2M_WR_TRACKER_FULL.MIRR", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x8", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Write Tracker Inserts : Channel 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x56", |
| "EventName": "UNC_M2M_WR_TRACKER_INSERTS.CH0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Write Tracker Inserts : Channel 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x56", |
| "EventName": "UNC_M2M_WR_TRACKER_INSERTS.CH1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Write Tracker Cycles Not Empty : Channel 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x4B", |
| "EventName": "UNC_M2M_WR_TRACKER_NE.CH0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Write Tracker Cycles Not Empty : Channel 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x4B", |
| "EventName": "UNC_M2M_WR_TRACKER_NE.CH1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Write Tracker Cycles Not Empty : Mirror", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x4B", |
| "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x8", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Write Tracker Cycles Not Empty", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x4B", |
| "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR_NONTGR", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x10", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Write Tracker Cycles Not Empty", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x4B", |
| "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR_PWR", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x20", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Write Tracker Non-Posted Inserts : Channel 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x63", |
| "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_INSERTS.CH0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Write Tracker Non-Posted Inserts : Channel 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x63", |
| "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_INSERTS.CH1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Write Tracker Non-Posted Occupancy : Channel 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x62", |
| "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_OCCUPANCY.CH0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Write Tracker Non-Posted Occupancy : Channel 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x62", |
| "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_OCCUPANCY.CH1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Write Tracker Occupancy : Channel 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x55", |
| "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.CH0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Write Tracker Occupancy : Channel 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x55", |
| "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.CH1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Write Tracker Occupancy : Mirror", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x55", |
| "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.MIRR", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x8", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Write Tracker Occupancy", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x55", |
| "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.MIRR_NONTGR", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x10", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Write Tracker Occupancy", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x55", |
| "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.MIRR_PWR", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x20", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Write Tracker Posted Inserts : Channel 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x5E", |
| "EventName": "UNC_M2M_WR_TRACKER_POSTED_INSERTS.CH0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Write Tracker Posted Inserts : Channel 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x5E", |
| "EventName": "UNC_M2M_WR_TRACKER_POSTED_INSERTS.CH1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Write Tracker Posted Occupancy : Channel 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x5D", |
| "EventName": "UNC_M2M_WR_TRACKER_POSTED_OCCUPANCY.CH0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Write Tracker Posted Occupancy : Channel 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x5D", |
| "EventName": "UNC_M2M_WR_TRACKER_POSTED_OCCUPANCY.CH1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "M2M" |
| }, |
| { |
| "BriefDescription": "Clockticks in the UBOX using a dedicated 48-bit Fixed Counter", |
| "Counter": "FIXED", |
| "EventCode": "0xff", |
| "EventName": "UNC_U_CLOCKTICKS", |
| "PerPkg": "1", |
| "Unit": "UBOX" |
| }, |
| { |
| "BriefDescription": "Message Received : Doorbell", |
| "Counter": "0,1", |
| "EventCode": "0x42", |
| "EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x8", |
| "Unit": "UBOX" |
| }, |
| { |
| "BriefDescription": "Message Received : Interrupt", |
| "Counter": "0,1", |
| "EventCode": "0x42", |
| "EventName": "UNC_U_EVENT_MSG.INT_PRIO", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Message Received : Interrupt : Interrupts", |
| "UMask": "0x10", |
| "Unit": "UBOX" |
| }, |
| { |
| "BriefDescription": "Message Received : IPI", |
| "Counter": "0,1", |
| "EventCode": "0x42", |
| "EventName": "UNC_U_EVENT_MSG.IPI_RCVD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Message Received : IPI : Inter Processor Interrupts", |
| "UMask": "0x4", |
| "Unit": "UBOX" |
| }, |
| { |
| "BriefDescription": "Message Received : MSI", |
| "Counter": "0,1", |
| "EventCode": "0x42", |
| "EventName": "UNC_U_EVENT_MSG.MSI_RCVD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Message Received : MSI : Message Signaled Interrupts - interrupts sent by devices (including PCIe via IOxAPIC) (Socket Mode only)", |
| "UMask": "0x2", |
| "Unit": "UBOX" |
| }, |
| { |
| "BriefDescription": "Message Received : VLW", |
| "Counter": "0,1", |
| "EventCode": "0x42", |
| "EventName": "UNC_U_EVENT_MSG.VLW_RCVD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Message Received : VLW : Virtual Logical Wire (legacy) message were received from Uncore.", |
| "UMask": "0x1", |
| "Unit": "UBOX" |
| }, |
| { |
| "BriefDescription": "IDI Lock/SplitLock Cycles", |
| "Counter": "0,1", |
| "EventCode": "0x44", |
| "EventName": "UNC_U_LOCK_CYCLES", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "IDI Lock/SplitLock Cycles : Number of times an IDI Lock/SplitLock sequence was started", |
| "Unit": "UBOX" |
| }, |
| { |
| "BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCB", |
| "Counter": "0,1", |
| "EventCode": "0x4D", |
| "EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCB", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "UBOX" |
| }, |
| { |
| "BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCS", |
| "Counter": "0,1", |
| "EventCode": "0x4D", |
| "EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "UBOX" |
| }, |
| { |
| "BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCB", |
| "Counter": "0,1", |
| "EventCode": "0x4D", |
| "EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCB", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x10", |
| "Unit": "UBOX" |
| }, |
| { |
| "BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCS", |
| "Counter": "0,1", |
| "EventCode": "0x4D", |
| "EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x20", |
| "Unit": "UBOX" |
| }, |
| { |
| "BriefDescription": "UNC_U_M2U_MISC2.RxC_CYCLES_EMPTY_BL", |
| "Counter": "0,1", |
| "EventCode": "0x4E", |
| "EventName": "UNC_U_M2U_MISC2.RxC_CYCLES_EMPTY_BL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "UBOX" |
| }, |
| { |
| "BriefDescription": "UNC_U_M2U_MISC2.RxC_CYCLES_FULL_BL", |
| "Counter": "0,1", |
| "EventCode": "0x4E", |
| "EventName": "UNC_U_M2U_MISC2.RxC_CYCLES_FULL_BL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "UBOX" |
| }, |
| { |
| "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCB", |
| "Counter": "0,1", |
| "EventCode": "0x4E", |
| "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCB", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x4", |
| "Unit": "UBOX" |
| }, |
| { |
| "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCS", |
| "Counter": "0,1", |
| "EventCode": "0x4E", |
| "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x8", |
| "Unit": "UBOX" |
| }, |
| { |
| "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AK", |
| "Counter": "0,1", |
| "EventCode": "0x4E", |
| "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AK", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x20", |
| "Unit": "UBOX" |
| }, |
| { |
| "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AKC", |
| "Counter": "0,1", |
| "EventCode": "0x4E", |
| "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AKC", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x40", |
| "Unit": "UBOX" |
| }, |
| { |
| "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_BL", |
| "Counter": "0,1", |
| "EventCode": "0x4E", |
| "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_BL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x10", |
| "Unit": "UBOX" |
| }, |
| { |
| "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_FULL_BL", |
| "Counter": "0,1", |
| "EventCode": "0x4E", |
| "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_FULL_BL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x80", |
| "Unit": "UBOX" |
| }, |
| { |
| "BriefDescription": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AK", |
| "Counter": "0,1", |
| "EventCode": "0x4F", |
| "EventName": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AK", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "UBOX" |
| }, |
| { |
| "BriefDescription": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AKC", |
| "Counter": "0,1", |
| "EventCode": "0x4F", |
| "EventName": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AKC", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "UBOX" |
| }, |
| { |
| "BriefDescription": "Cycles PHOLD Assert to Ack : Assert to ACK", |
| "Counter": "0,1", |
| "EventCode": "0x45", |
| "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles PHOLD Assert to Ack : Assert to ACK : PHOLD cycles.", |
| "UMask": "0x1", |
| "Unit": "UBOX" |
| }, |
| { |
| "BriefDescription": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY", |
| "Counter": "0,1", |
| "EventCode": "0x4C", |
| "EventName": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x4", |
| "Unit": "UBOX" |
| }, |
| { |
| "BriefDescription": "UNC_U_RACU_DRNG.RDRAND", |
| "Counter": "0,1", |
| "EventCode": "0x4C", |
| "EventName": "UNC_U_RACU_DRNG.RDRAND", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "UBOX" |
| }, |
| { |
| "BriefDescription": "UNC_U_RACU_DRNG.RDSEED", |
| "Counter": "0,1", |
| "EventCode": "0x4C", |
| "EventName": "UNC_U_RACU_DRNG.RDSEED", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "UBOX" |
| }, |
| { |
| "BriefDescription": "RACU Request", |
| "Counter": "0,1", |
| "EventCode": "0x46", |
| "EventName": "UNC_U_RACU_REQUESTS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "RACU Request : Number outstanding register requests within message channel tracker", |
| "Unit": "UBOX" |
| } |
| ] |
