| [ |
| { |
| "BriefDescription": "PCI Express bandwidth reading at IIO. Derived from unc_iio_data_req_of_cpu.mem_read.part0", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "LLC_MISSES.PCIE_READ", |
| "FCMask": "0x07", |
| "Filter": "ch_mask=0x1f", |
| "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", |
| "MetricName": "LLC_MISSES.PCIE_READ", |
| "PerPkg": "1", |
| "PortMask": "0x01", |
| "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", |
| "ScaleUnit": "4Bytes", |
| "UMask": "0x4", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "PCI Express bandwidth writing at IIO. Derived from unc_iio_data_req_of_cpu.mem_write.part0", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "LLC_MISSES.PCIE_WRITE", |
| "FCMask": "0x07", |
| "Filter": "ch_mask=0x1f", |
| "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", |
| "MetricName": "LLC_MISSES.PCIE_WRITE", |
| "PerPkg": "1", |
| "PortMask": "0x01", |
| "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", |
| "ScaleUnit": "4Bytes", |
| "UMask": "0x1", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", |
| "Counter": "1", |
| "EventCode": "0xff", |
| "EventName": "UNC_IIO_BANDWIDTH_IN.PART0_FREERUN", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x20", |
| "Unit": "iio_free_running" |
| }, |
| { |
| "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", |
| "Counter": "2", |
| "EventCode": "0xff", |
| "EventName": "UNC_IIO_BANDWIDTH_IN.PART1_FREERUN", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x21", |
| "Unit": "iio_free_running" |
| }, |
| { |
| "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", |
| "Counter": "3", |
| "EventCode": "0xff", |
| "EventName": "UNC_IIO_BANDWIDTH_IN.PART2_FREERUN", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x22", |
| "Unit": "iio_free_running" |
| }, |
| { |
| "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", |
| "Counter": "4", |
| "EventCode": "0xff", |
| "EventName": "UNC_IIO_BANDWIDTH_IN.PART3_FREERUN", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x23", |
| "Unit": "iio_free_running" |
| }, |
| { |
| "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", |
| "Counter": "5", |
| "EventCode": "0xff", |
| "EventName": "UNC_IIO_BANDWIDTH_IN.PART4_FREERUN", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x24", |
| "Unit": "iio_free_running" |
| }, |
| { |
| "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", |
| "Counter": "6", |
| "EventCode": "0xff", |
| "EventName": "UNC_IIO_BANDWIDTH_IN.PART5_FREERUN", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x25", |
| "Unit": "iio_free_running" |
| }, |
| { |
| "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", |
| "Counter": "7", |
| "EventCode": "0xff", |
| "EventName": "UNC_IIO_BANDWIDTH_IN.PART6_FREERUN", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x26", |
| "Unit": "iio_free_running" |
| }, |
| { |
| "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", |
| "Counter": "8", |
| "EventCode": "0xff", |
| "EventName": "UNC_IIO_BANDWIDTH_IN.PART7_FREERUN", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x27", |
| "Unit": "iio_free_running" |
| }, |
| { |
| "BriefDescription": "Clockticks of the integrated IO (IIO) traffic controller", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x01", |
| "EventName": "UNC_IIO_CLOCKTICKS", |
| "PerPkg": "1", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Free running counter that increments for IIO clocktick", |
| "Counter": "0", |
| "EventCode": "0xff", |
| "EventName": "UNC_IIO_CLOCKTICKS_FREERUN", |
| "PerPkg": "1", |
| "PublicDescription": "Free running counter that increments for integrated IO (IIO) traffic controller clockticks", |
| "UMask": "0x10", |
| "Unit": "iio_free_running" |
| }, |
| { |
| "BriefDescription": "PCIe Completion Buffer Inserts : All Ports", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xC2", |
| "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL", |
| "Experimental": "1", |
| "FCMask": "0x04", |
| "PerPkg": "1", |
| "PortMask": "0xFF", |
| "UMask": "0x3", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-7", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xc2", |
| "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL_PARTS", |
| "FCMask": "0x04", |
| "PerPkg": "1", |
| "PortMask": "0xff", |
| "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0-7", |
| "UMask": "0x3", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xc2", |
| "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0", |
| "FCMask": "0x04", |
| "PerPkg": "1", |
| "PortMask": "0x01", |
| "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", |
| "UMask": "0x3", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xc2", |
| "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1", |
| "FCMask": "0x04", |
| "PerPkg": "1", |
| "PortMask": "0x02", |
| "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 1", |
| "UMask": "0x3", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 2", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xc2", |
| "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2", |
| "FCMask": "0x04", |
| "PerPkg": "1", |
| "PortMask": "0x04", |
| "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 2", |
| "UMask": "0x3", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 3", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xc2", |
| "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3", |
| "FCMask": "0x04", |
| "PerPkg": "1", |
| "PortMask": "0x08", |
| "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 3", |
| "UMask": "0x3", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 4", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xc2", |
| "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART4", |
| "FCMask": "0x04", |
| "PerPkg": "1", |
| "PortMask": "0x10", |
| "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 4", |
| "UMask": "0x3", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 5", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xc2", |
| "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART5", |
| "FCMask": "0x04", |
| "PerPkg": "1", |
| "PortMask": "0x20", |
| "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 5", |
| "UMask": "0x3", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 6", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xc2", |
| "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART6", |
| "FCMask": "0x04", |
| "PerPkg": "1", |
| "PortMask": "0x40", |
| "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 6", |
| "UMask": "0x3", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 7", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xc2", |
| "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART7", |
| "FCMask": "0x04", |
| "PerPkg": "1", |
| "PortMask": "0x80", |
| "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 7", |
| "UMask": "0x3", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 0-7", |
| "Counter": "2,3", |
| "EventCode": "0xD5", |
| "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL", |
| "Experimental": "1", |
| "FCMask": "0x04", |
| "PerPkg": "1", |
| "PublicDescription": "PCIe Completion Buffer Occupancy : Part 0-7", |
| "UMask": "0xff", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 0-7", |
| "Counter": "2,3", |
| "EventCode": "0xd5", |
| "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS", |
| "FCMask": "0x04", |
| "PerPkg": "1", |
| "PublicDescription": "PCIe Completion Buffer Occupancy : Part 0-7", |
| "UMask": "0xff", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 0", |
| "Counter": "2,3", |
| "EventCode": "0xd5", |
| "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART0", |
| "FCMask": "0x04", |
| "PerPkg": "1", |
| "PublicDescription": "PCIe Completion Buffer Occupancy : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", |
| "UMask": "0x1", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 1", |
| "Counter": "2,3", |
| "EventCode": "0xd5", |
| "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART1", |
| "FCMask": "0x04", |
| "PerPkg": "1", |
| "PublicDescription": "PCIe Completion Buffer Occupancy : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 1", |
| "UMask": "0x2", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 2", |
| "Counter": "2,3", |
| "EventCode": "0xd5", |
| "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART2", |
| "FCMask": "0x04", |
| "PerPkg": "1", |
| "PublicDescription": "PCIe Completion Buffer Occupancy : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 2", |
| "UMask": "0x4", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 3", |
| "Counter": "2,3", |
| "EventCode": "0xd5", |
| "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART3", |
| "FCMask": "0x04", |
| "PerPkg": "1", |
| "PublicDescription": "PCIe Completion Buffer Occupancy : Part 3 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 3", |
| "UMask": "0x8", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 4", |
| "Counter": "2,3", |
| "EventCode": "0xd5", |
| "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART4", |
| "FCMask": "0x04", |
| "PerPkg": "1", |
| "PublicDescription": "PCIe Completion Buffer Occupancy : Part 4 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 4", |
| "UMask": "0x10", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 5", |
| "Counter": "2,3", |
| "EventCode": "0xd5", |
| "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART5", |
| "FCMask": "0x04", |
| "PerPkg": "1", |
| "PublicDescription": "PCIe Completion Buffer Occupancy : Part 5 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 5", |
| "UMask": "0x20", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 6", |
| "Counter": "2,3", |
| "EventCode": "0xd5", |
| "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART6", |
| "FCMask": "0x04", |
| "PerPkg": "1", |
| "PublicDescription": "PCIe Completion Buffer Occupancy : Part 6 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 6", |
| "UMask": "0x40", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 7", |
| "Counter": "2,3", |
| "EventCode": "0xd5", |
| "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART7", |
| "FCMask": "0x04", |
| "PerPkg": "1", |
| "PublicDescription": "PCIe Completion Buffer Occupancy : Part 7 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 7", |
| "UMask": "0x80", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.IOMMU0", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x100", |
| "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0", |
| "UMask": "0x40", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.IOMMU1", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x200", |
| "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1", |
| "UMask": "0x40", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART0", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x01", |
| "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", |
| "UMask": "0x40", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART1", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x02", |
| "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", |
| "UMask": "0x40", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART2", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x04", |
| "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", |
| "UMask": "0x40", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART3", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x08", |
| "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", |
| "UMask": "0x40", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART4", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x10", |
| "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", |
| "UMask": "0x40", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART5", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x20", |
| "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", |
| "UMask": "0x40", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART6", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x40", |
| "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", |
| "UMask": "0x40", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART7", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x80", |
| "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", |
| "UMask": "0x40", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.IOMMU0", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x100", |
| "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0", |
| "UMask": "0x10", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.IOMMU1", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x200", |
| "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1", |
| "UMask": "0x10", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART0", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x01", |
| "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", |
| "UMask": "0x10", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART1", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x02", |
| "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", |
| "UMask": "0x10", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART2", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x04", |
| "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", |
| "UMask": "0x10", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART3", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x08", |
| "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", |
| "UMask": "0x10", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART4", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x10", |
| "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", |
| "UMask": "0x10", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART5", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x20", |
| "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", |
| "UMask": "0x10", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART6", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x40", |
| "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", |
| "UMask": "0x10", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART7", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x80", |
| "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", |
| "UMask": "0x10", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.IOMMU0", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x100", |
| "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0", |
| "UMask": "0x80", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.IOMMU1", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x200", |
| "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1", |
| "UMask": "0x80", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART0", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x01", |
| "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", |
| "UMask": "0x80", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART1", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x02", |
| "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", |
| "UMask": "0x80", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART2", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x04", |
| "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", |
| "UMask": "0x80", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART3", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x08", |
| "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", |
| "UMask": "0x80", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART4", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x10", |
| "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", |
| "UMask": "0x80", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART5", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x20", |
| "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", |
| "UMask": "0x80", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART6", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x40", |
| "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", |
| "UMask": "0x80", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART7", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x80", |
| "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", |
| "UMask": "0x80", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.IOMMU0", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x100", |
| "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0", |
| "UMask": "0x20", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.IOMMU1", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x200", |
| "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1", |
| "UMask": "0x20", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART0", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x01", |
| "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", |
| "UMask": "0x20", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART1", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x02", |
| "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", |
| "UMask": "0x20", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART2", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x04", |
| "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", |
| "UMask": "0x20", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART3", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x08", |
| "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", |
| "UMask": "0x20", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART4", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x10", |
| "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", |
| "UMask": "0x20", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART5", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x20", |
| "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", |
| "UMask": "0x20", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART6", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x40", |
| "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", |
| "UMask": "0x20", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART7", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x80", |
| "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", |
| "UMask": "0x20", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.IOMMU0", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x100", |
| "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0", |
| "UMask": "0x4", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.IOMMU1", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x200", |
| "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1", |
| "UMask": "0x4", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", |
| "Counter": "2,3", |
| "EventCode": "0xc0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x01", |
| "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", |
| "UMask": "0x4", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", |
| "Counter": "2,3", |
| "EventCode": "0xc0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x02", |
| "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", |
| "UMask": "0x4", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", |
| "Counter": "2,3", |
| "EventCode": "0xc0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x04", |
| "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", |
| "UMask": "0x4", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", |
| "Counter": "2,3", |
| "EventCode": "0xc0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x08", |
| "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", |
| "UMask": "0x4", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", |
| "Counter": "2,3", |
| "EventCode": "0xc0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART4", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x10", |
| "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", |
| "UMask": "0x4", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", |
| "Counter": "2,3", |
| "EventCode": "0xc0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART5", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x20", |
| "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", |
| "UMask": "0x4", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", |
| "Counter": "2,3", |
| "EventCode": "0xc0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART6", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x40", |
| "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", |
| "UMask": "0x4", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", |
| "Counter": "2,3", |
| "EventCode": "0xc0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART7", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x80", |
| "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", |
| "UMask": "0x4", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.IOMMU0", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x100", |
| "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0", |
| "UMask": "0x1", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.IOMMU1", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x200", |
| "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1", |
| "UMask": "0x1", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x01", |
| "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", |
| "UMask": "0x1", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x02", |
| "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", |
| "UMask": "0x1", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x04", |
| "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", |
| "UMask": "0x1", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x08", |
| "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", |
| "UMask": "0x1", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART4", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x10", |
| "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", |
| "UMask": "0x1", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART5", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x20", |
| "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", |
| "UMask": "0x1", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART6", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x40", |
| "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", |
| "UMask": "0x1", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART7", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x80", |
| "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", |
| "UMask": "0x1", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.IOMMU0", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x100", |
| "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0", |
| "UMask": "0x8", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.IOMMU1", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x200", |
| "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1", |
| "UMask": "0x8", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART0", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x01", |
| "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", |
| "UMask": "0x8", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART1", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x02", |
| "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", |
| "UMask": "0x8", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART2", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x04", |
| "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", |
| "UMask": "0x8", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART3", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x08", |
| "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", |
| "UMask": "0x8", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART4", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x10", |
| "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", |
| "UMask": "0x8", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART5", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x20", |
| "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", |
| "UMask": "0x8", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART6", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x40", |
| "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", |
| "UMask": "0x8", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART7", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x80", |
| "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", |
| "UMask": "0x8", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.IOMMU0", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x100", |
| "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0", |
| "UMask": "0x2", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.IOMMU1", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x200", |
| "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1", |
| "UMask": "0x2", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART0", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x01", |
| "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", |
| "UMask": "0x2", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART1", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x02", |
| "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", |
| "UMask": "0x2", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART2", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x04", |
| "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", |
| "UMask": "0x2", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART3", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x08", |
| "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", |
| "UMask": "0x2", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART4", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x10", |
| "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", |
| "UMask": "0x2", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART5", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x20", |
| "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", |
| "UMask": "0x2", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART6", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x40", |
| "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", |
| "UMask": "0x2", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.", |
| "Counter": "2,3", |
| "EventCode": "0xC0", |
| "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART7", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x80", |
| "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", |
| "UMask": "0x2", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.IOMMU0", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x100", |
| "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0", |
| "UMask": "0x10", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.IOMMU1", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x200", |
| "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1", |
| "UMask": "0x10", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART0", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x01", |
| "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", |
| "UMask": "0x10", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART1", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x02", |
| "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", |
| "UMask": "0x10", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART2", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x04", |
| "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", |
| "UMask": "0x10", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART3", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x08", |
| "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", |
| "UMask": "0x10", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART4", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x10", |
| "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", |
| "UMask": "0x10", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART5", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x20", |
| "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", |
| "UMask": "0x10", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART6", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x40", |
| "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", |
| "UMask": "0x10", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART7", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x80", |
| "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", |
| "UMask": "0x10", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.IOMMU0", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x100", |
| "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0", |
| "UMask": "0x80", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.IOMMU1", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x200", |
| "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1", |
| "UMask": "0x80", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART0", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x01", |
| "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", |
| "UMask": "0x80", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x02", |
| "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", |
| "UMask": "0x80", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART2", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x04", |
| "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", |
| "UMask": "0x80", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART3", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x08", |
| "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", |
| "UMask": "0x80", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART4", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x10", |
| "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", |
| "UMask": "0x80", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART5", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x20", |
| "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", |
| "UMask": "0x80", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART6", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x40", |
| "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", |
| "UMask": "0x80", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART7", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x80", |
| "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", |
| "UMask": "0x80", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.IOMMU0", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x100", |
| "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0", |
| "UMask": "0x4", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.IOMMU1", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x200", |
| "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1", |
| "UMask": "0x4", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "PCI Express bandwidth reading at IIO, part 0", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x01", |
| "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", |
| "UMask": "0x4", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "PCI Express bandwidth reading at IIO, part 1", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x02", |
| "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", |
| "UMask": "0x4", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "PCI Express bandwidth reading at IIO, part 2", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x04", |
| "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", |
| "UMask": "0x4", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "PCI Express bandwidth reading at IIO, part 3", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x08", |
| "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", |
| "UMask": "0x4", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART4", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x10", |
| "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", |
| "UMask": "0x4", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART5", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x20", |
| "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", |
| "UMask": "0x4", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART6", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x40", |
| "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", |
| "UMask": "0x4", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART7", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x80", |
| "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", |
| "UMask": "0x4", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.IOMMU0", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x100", |
| "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0", |
| "UMask": "0x1", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.IOMMU1", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x200", |
| "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1", |
| "UMask": "0x1", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "PCI Express bandwidth writing at IIO, part 0", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x01", |
| "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", |
| "UMask": "0x1", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "PCI Express bandwidth writing at IIO, part 1", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x02", |
| "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", |
| "UMask": "0x1", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "PCI Express bandwidth writing at IIO, part 2", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x04", |
| "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", |
| "UMask": "0x1", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "PCI Express bandwidth writing at IIO, part 3", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x08", |
| "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", |
| "UMask": "0x1", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART4", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x10", |
| "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", |
| "UMask": "0x1", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART5", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x20", |
| "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", |
| "UMask": "0x1", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART6", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x40", |
| "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", |
| "UMask": "0x1", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART7", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x80", |
| "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", |
| "UMask": "0x1", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested of the CPU : Messages", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.IOMMU0", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x100", |
| "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0", |
| "UMask": "0x40", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested of the CPU : Messages", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.IOMMU1", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x200", |
| "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1", |
| "UMask": "0x40", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested of the CPU : Messages", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART0", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x01", |
| "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", |
| "UMask": "0x40", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested of the CPU : Messages", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART1", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x02", |
| "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", |
| "UMask": "0x40", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested of the CPU : Messages", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART2", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x04", |
| "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", |
| "UMask": "0x40", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested of the CPU : Messages", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART3", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x08", |
| "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", |
| "UMask": "0x40", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested of the CPU : Messages", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART4", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x10", |
| "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", |
| "UMask": "0x40", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested of the CPU : Messages", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART5", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x20", |
| "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", |
| "UMask": "0x40", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested of the CPU : Messages", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART6", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x40", |
| "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", |
| "UMask": "0x40", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested of the CPU : Messages", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART7", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x80", |
| "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", |
| "UMask": "0x40", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.IOMMU0", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x100", |
| "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0", |
| "UMask": "0x8", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.IOMMU1", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x200", |
| "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1", |
| "UMask": "0x8", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART0", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x01", |
| "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", |
| "UMask": "0x8", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART1", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x02", |
| "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", |
| "UMask": "0x8", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART2", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x04", |
| "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", |
| "UMask": "0x8", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART3", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x08", |
| "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", |
| "UMask": "0x8", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART4", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x10", |
| "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", |
| "UMask": "0x8", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART5", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x20", |
| "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", |
| "UMask": "0x8", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART6", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x40", |
| "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", |
| "UMask": "0x8", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART7", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x80", |
| "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", |
| "UMask": "0x8", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.IOMMU0", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x100", |
| "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0", |
| "UMask": "0x2", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.IOMMU1", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x200", |
| "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1", |
| "UMask": "0x2", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x01", |
| "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", |
| "UMask": "0x2", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x02", |
| "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", |
| "UMask": "0x2", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x04", |
| "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", |
| "UMask": "0x2", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x08", |
| "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", |
| "UMask": "0x2", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART4", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x10", |
| "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", |
| "UMask": "0x2", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART5", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x20", |
| "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", |
| "UMask": "0x2", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART6", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x40", |
| "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", |
| "UMask": "0x2", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", |
| "Counter": "0,1", |
| "EventCode": "0x83", |
| "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART7", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x80", |
| "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", |
| "UMask": "0x2", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Incoming arbitration requests : Passing data to be written", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x86", |
| "EventName": "UNC_IIO_INBOUND_ARB_REQ.DATA", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0xFF", |
| "PublicDescription": "Incoming arbitration requests : Passing data to be written : How often different queues (e.g. channel / fc) ask to send request into pipeline : Only for posted requests", |
| "UMask": "0x20", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Incoming arbitration requests : Issuing final read or write of line", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x86", |
| "EventName": "UNC_IIO_INBOUND_ARB_REQ.FINAL_RD_WR", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0xFF", |
| "PublicDescription": "Incoming arbitration requests : Issuing final read or write of line : How often different queues (e.g. channel / fc) ask to send request into pipeline", |
| "UMask": "0x8", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Incoming arbitration requests : Processing response from IOMMU", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x86", |
| "EventName": "UNC_IIO_INBOUND_ARB_REQ.IOMMU_HIT", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0xFF", |
| "PublicDescription": "Incoming arbitration requests : Processing response from IOMMU : How often different queues (e.g. channel / fc) ask to send request into pipeline", |
| "UMask": "0x2", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Incoming arbitration requests : Issuing to IOMMU", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x86", |
| "EventName": "UNC_IIO_INBOUND_ARB_REQ.IOMMU_REQ", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0xFF", |
| "PublicDescription": "Incoming arbitration requests : Issuing to IOMMU : How often different queues (e.g. channel / fc) ask to send request into pipeline", |
| "UMask": "0x1", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Incoming arbitration requests : Request Ownership", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x86", |
| "EventName": "UNC_IIO_INBOUND_ARB_REQ.REQ_OWN", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0xFF", |
| "PublicDescription": "Incoming arbitration requests : Request Ownership : How often different queues (e.g. channel / fc) ask to send request into pipeline : Only for posted requests", |
| "UMask": "0x4", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Incoming arbitration requests : Writing line", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x86", |
| "EventName": "UNC_IIO_INBOUND_ARB_REQ.WR", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0xFF", |
| "PublicDescription": "Incoming arbitration requests : Writing line : How often different queues (e.g. channel / fc) ask to send request into pipeline : Only for posted requests", |
| "UMask": "0x10", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Incoming arbitration requests granted : Passing data to be written", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x87", |
| "EventName": "UNC_IIO_INBOUND_ARB_WON.DATA", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0xFF", |
| "PublicDescription": "Incoming arbitration requests granted : Passing data to be written : How often different queues (e.g. channel / fc) are allowed to send request into pipeline : Only for posted requests", |
| "UMask": "0x20", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Incoming arbitration requests granted : Issuing final read or write of line", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x87", |
| "EventName": "UNC_IIO_INBOUND_ARB_WON.FINAL_RD_WR", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0xFF", |
| "PublicDescription": "Incoming arbitration requests granted : Issuing final read or write of line : How often different queues (e.g. channel / fc) are allowed to send request into pipeline", |
| "UMask": "0x8", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Incoming arbitration requests granted : Processing response from IOMMU", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x87", |
| "EventName": "UNC_IIO_INBOUND_ARB_WON.IOMMU_HIT", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0xFF", |
| "PublicDescription": "Incoming arbitration requests granted : Processing response from IOMMU : How often different queues (e.g. channel / fc) are allowed to send request into pipeline", |
| "UMask": "0x2", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Incoming arbitration requests granted : Issuing to IOMMU", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x87", |
| "EventName": "UNC_IIO_INBOUND_ARB_WON.IOMMU_REQ", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0xFF", |
| "PublicDescription": "Incoming arbitration requests granted : Issuing to IOMMU : How often different queues (e.g. channel / fc) are allowed to send request into pipeline", |
| "UMask": "0x1", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Incoming arbitration requests granted : Request Ownership", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x87", |
| "EventName": "UNC_IIO_INBOUND_ARB_WON.REQ_OWN", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0xFF", |
| "PublicDescription": "Incoming arbitration requests granted : Request Ownership : How often different queues (e.g. channel / fc) are allowed to send request into pipeline : Only for posted requests", |
| "UMask": "0x4", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Incoming arbitration requests granted : Writing line", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x87", |
| "EventName": "UNC_IIO_INBOUND_ARB_WON.WR", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0xFF", |
| "PublicDescription": "Incoming arbitration requests granted : Writing line : How often different queues (e.g. channel / fc) are allowed to send request into pipeline : Only for posted requests", |
| "UMask": "0x10", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": ": IOTLB Hits to a 1G Page", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x40", |
| "EventName": "UNC_IIO_IOMMU0.1G_HITS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": ": IOTLB Hits to a 1G Page : Counts if a transaction to a 1G page, on its first lookup, hits the IOTLB.", |
| "UMask": "0x10", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": ": IOTLB Hits to a 2M Page", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x40", |
| "EventName": "UNC_IIO_IOMMU0.2M_HITS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": ": IOTLB Hits to a 2M Page : Counts if a transaction to a 2M page, on its first lookup, hits the IOTLB.", |
| "UMask": "0x8", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": ": IOTLB Hits to a 4K Page", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x40", |
| "EventName": "UNC_IIO_IOMMU0.4K_HITS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": ": IOTLB Hits to a 4K Page : Counts if a transaction to a 4K page, on its first lookup, hits the IOTLB.", |
| "UMask": "0x4", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": ": IOTLB lookups all", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x40", |
| "EventName": "UNC_IIO_IOMMU0.ALL_LOOKUPS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": ": IOTLB lookups all : Some transactions have to look up IOTLB multiple times. Counts every time a request looks up IOTLB.", |
| "UMask": "0x2", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": ": Context cache hits", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x40", |
| "EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_HITS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": ": Context cache hits : Counts each time a first look up of the transaction hits the RCC.", |
| "UMask": "0x80", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": ": Context cache lookups", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x40", |
| "EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_LOOKUPS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": ": Context cache lookups : Counts each time a transaction looks up root context cache.", |
| "UMask": "0x40", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": ": IOTLB lookups first", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x40", |
| "EventName": "UNC_IIO_IOMMU0.FIRST_LOOKUPS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": ": IOTLB lookups first : Some transactions have to look up IOTLB multiple times. Counts the first time a request looks up IOTLB.", |
| "UMask": "0x1", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": ": IOTLB Fills (same as IOTLB miss)", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x40", |
| "EventName": "UNC_IIO_IOMMU0.MISSES", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": ": IOTLB Fills (same as IOTLB miss) : When a transaction misses IOTLB, it does a page walk to look up memory and bring in the relevant page translation. Counts when this page translation is written to IOTLB.", |
| "UMask": "0x20", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": ": Cycles PWT full", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x41", |
| "EventName": "UNC_IIO_IOMMU1.CYC_PWT_FULL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": ": Cycles PWT full : Counts cycles the IOMMU has reached its maximum limit for outstanding page walks.", |
| "UMask": "0x80", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": ": IOMMU memory access", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x41", |
| "EventName": "UNC_IIO_IOMMU1.NUM_MEM_ACCESSES", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": ": IOMMU memory access : IOMMU sends out memory fetches when it misses the cache look up which is indicated by this signal. M2IOSF only uses low priority channel", |
| "UMask": "0x40", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": ": PWC Hit to a 1G page", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x41", |
| "EventName": "UNC_IIO_IOMMU1.PWC_1G_HITS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": ": PWC Hit to a 1G page : Counts each time a transaction's first look up hits the SLPWC at the 1G level", |
| "UMask": "0x8", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": ": PWC Hit to a 2M page", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x41", |
| "EventName": "UNC_IIO_IOMMU1.PWC_2M_HITS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": ": PWC Hit to a 2M page : Counts each time a transaction's first look up hits the SLPWC at the 2M level", |
| "UMask": "0x4", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": ": PWC Hit to a 4K page", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x41", |
| "EventName": "UNC_IIO_IOMMU1.PWC_4K_HITS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": ": PWC Hit to a 4K page : Counts each time a transaction's first look up hits the SLPWC at the 4K level", |
| "UMask": "0x2", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": ": PWT Hit to a 256T page", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x41", |
| "EventName": "UNC_IIO_IOMMU1.PWC_512G_HITS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": ": PWT Hit to a 256T page : Counts each time a transaction's first look up hits the SLPWC at the 512G level", |
| "UMask": "0x10", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": ": PageWalk cache fill", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x41", |
| "EventName": "UNC_IIO_IOMMU1.PWC_CACHE_FILLS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": ": PageWalk cache fill : When a transaction misses SLPWC, it does a page walk to look up memory and bring in the relevant page translation. When this page translation is written to SLPWC, ObsPwcFillValid_nnnH is asserted.", |
| "UMask": "0x20", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": ": PageWalk cache lookup", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x41", |
| "EventName": "UNC_IIO_IOMMU1.PWT_CACHE_LOOKUPS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": ": PageWalk cache lookup : Counts each time a transaction looks up second level page walk cache.", |
| "UMask": "0x1", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": ": Interrupt Entry cache hit", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x43", |
| "EventName": "UNC_IIO_IOMMU3.INT_CACHE_HITS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": ": Interrupt Entry cache hit : Counts each time a transaction's first look up hits the IEC.", |
| "UMask": "0x80", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": ": Interrupt Entry cache lookup", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x43", |
| "EventName": "UNC_IIO_IOMMU3.INT_CACHE_LOOKUPS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": ": Interrupt Entry cache lookup : Counts the number of transaction looks up that interrupt remapping cache.", |
| "UMask": "0x40", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": ": Device-selective Context cache invalidation cycles", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x43", |
| "EventName": "UNC_IIO_IOMMU3.NUM_CTXT_CACHE_INVAL_DEVICE", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": ": Device-selective Context cache invalidation cycles : Counts number of Device selective context cache invalidation events", |
| "UMask": "0x20", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": ": Domain-selective Context cache invalidation cycles", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x43", |
| "EventName": "UNC_IIO_IOMMU3.NUM_CTXT_CACHE_INVAL_DOMAIN", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": ": Domain-selective Context cache invalidation cycles : Counts number of Domain selective context cache invalidation events", |
| "UMask": "0x10", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": ": Context cache global invalidation cycles", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x43", |
| "EventName": "UNC_IIO_IOMMU3.NUM_CTXT_CACHE_INVAL_GBL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": ": Context cache global invalidation cycles : Counts number of Context Cache global invalidation events", |
| "UMask": "0x8", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": ": Domain-selective IOTLB invalidation cycles", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x43", |
| "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_DOMAIN", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": ": Domain-selective IOTLB invalidation cycles : Counts number of Domain selective invalidation events", |
| "UMask": "0x2", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": ": Global IOTLB invalidation cycles", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x43", |
| "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_GBL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": ": Global IOTLB invalidation cycles : Indicates that IOMMU is doing global invalidation.", |
| "UMask": "0x1", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": ": Page-selective IOTLB invalidation cycles", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x43", |
| "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_PAGE", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": ": Page-selective IOTLB invalidation cycles : Counts number of Page-selective within Domain Invalidation events", |
| "UMask": "0x4", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus", |
| "Counter": "0,1", |
| "EventCode": "0x02", |
| "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "AND Mask/match for debug bus : Non-PCIE bus : Asserted if all bits specified by mask match", |
| "UMask": "0x1", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus and PCIE bus", |
| "Counter": "0,1", |
| "EventCode": "0x02", |
| "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_BUS1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "AND Mask/match for debug bus : Non-PCIE bus and PCIE bus : Asserted if all bits specified by mask match", |
| "UMask": "0x8", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus and !(PCIE bus)", |
| "Counter": "0,1", |
| "EventCode": "0x02", |
| "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_NOT_BUS1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "AND Mask/match for debug bus : Non-PCIE bus and !(PCIE bus) : Asserted if all bits specified by mask match", |
| "UMask": "0x4", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "AND Mask/match for debug bus : PCIE bus", |
| "Counter": "0,1", |
| "EventCode": "0x02", |
| "EventName": "UNC_IIO_MASK_MATCH_AND.BUS1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "AND Mask/match for debug bus : PCIE bus : Asserted if all bits specified by mask match", |
| "UMask": "0x2", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "AND Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus", |
| "Counter": "0,1", |
| "EventCode": "0x02", |
| "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_BUS1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "AND Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus : Asserted if all bits specified by mask match", |
| "UMask": "0x10", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "AND Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus)", |
| "Counter": "0,1", |
| "EventCode": "0x02", |
| "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_NOT_BUS1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "AND Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus) : Asserted if all bits specified by mask match", |
| "UMask": "0x20", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus", |
| "Counter": "0,1", |
| "EventCode": "0x03", |
| "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "OR Mask/match for debug bus : Non-PCIE bus : Asserted if any bits specified by mask match", |
| "UMask": "0x1", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus and PCIE bus", |
| "Counter": "0,1", |
| "EventCode": "0x03", |
| "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_BUS1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "OR Mask/match for debug bus : Non-PCIE bus and PCIE bus : Asserted if any bits specified by mask match", |
| "UMask": "0x8", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus and !(PCIE bus)", |
| "Counter": "0,1", |
| "EventCode": "0x03", |
| "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_NOT_BUS1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "OR Mask/match for debug bus : Non-PCIE bus and !(PCIE bus) : Asserted if any bits specified by mask match", |
| "UMask": "0x4", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "OR Mask/match for debug bus : PCIE bus", |
| "Counter": "0,1", |
| "EventCode": "0x03", |
| "EventName": "UNC_IIO_MASK_MATCH_OR.BUS1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "OR Mask/match for debug bus : PCIE bus : Asserted if any bits specified by mask match", |
| "UMask": "0x2", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "OR Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus", |
| "Counter": "0,1", |
| "EventCode": "0x03", |
| "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_BUS1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "OR Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus : Asserted if any bits specified by mask match", |
| "UMask": "0x10", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "OR Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus)", |
| "Counter": "0,1", |
| "EventCode": "0x03", |
| "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_NOT_BUS1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "OR Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus) : Asserted if any bits specified by mask match", |
| "UMask": "0x20", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Counting disabled", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x80", |
| "EventName": "UNC_IIO_NOTHING", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Occupancy of outbound request queue : To device", |
| "Counter": "2,3", |
| "EventCode": "0xC5", |
| "EventName": "UNC_IIO_NUM_OUSTANDING_REQ_FROM_CPU.TO_IO", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0xFF", |
| "PublicDescription": "Occupancy of outbound request queue : To device : Counts number of outbound requests/completions IIO is currently processing", |
| "UMask": "0x8", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": ": Passing data to be written", |
| "Counter": "2,3", |
| "EventCode": "0x88", |
| "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.DATA", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0xFF", |
| "PublicDescription": ": Passing data to be written : Only for posted requests", |
| "UMask": "0x20", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": ": Issuing final read or write of line", |
| "Counter": "2,3", |
| "EventCode": "0x88", |
| "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.FINAL_RD_WR", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0xFF", |
| "UMask": "0x8", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": ": Processing response from IOMMU", |
| "Counter": "2,3", |
| "EventCode": "0x88", |
| "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.IOMMU_HIT", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0xFF", |
| "UMask": "0x2", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": ": Issuing to IOMMU", |
| "Counter": "2,3", |
| "EventCode": "0x88", |
| "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.IOMMU_REQ", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0xFF", |
| "UMask": "0x1", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": ": Request Ownership", |
| "Counter": "2,3", |
| "EventCode": "0x88", |
| "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.REQ_OWN", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0xFF", |
| "PublicDescription": ": Request Ownership : Only for posted requests", |
| "UMask": "0x4", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": ": Writing line", |
| "Counter": "2,3", |
| "EventCode": "0x88", |
| "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.WR", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0xFF", |
| "PublicDescription": ": Writing line : Only for posted requests", |
| "UMask": "0x10", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number requests sent to PCIe from main die : From ITC", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xC2", |
| "EventName": "UNC_IIO_NUM_REQ_FROM_CPU.ITC", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0xFF", |
| "PublicDescription": "Number requests sent to PCIe from main die : From ITC : Confined P2P", |
| "UMask": "0x2", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number requests sent to PCIe from main die : Completion allocations", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xc2", |
| "EventName": "UNC_IIO_NUM_REQ_FROM_CPU.PREALLOC", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0xFF", |
| "UMask": "0x4", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number requests PCIe makes of the main die : Drop request", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x85", |
| "EventName": "UNC_IIO_NUM_REQ_OF_CPU.ALL.DROP", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0xFF", |
| "PublicDescription": "Number requests PCIe makes of the main die : Drop request : Counts full PCIe requests before they're broken into a series of cache-line size requests as measured by DATA_REQ_OF_CPU and TXN_REQ_OF_CPU. : Packet error detected, must be dropped", |
| "UMask": "0x2", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number requests PCIe makes of the main die : All", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x85", |
| "EventName": "UNC_IIO_NUM_REQ_OF_CPU.COMMIT.ALL", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0xFF", |
| "PublicDescription": "Number requests PCIe makes of the main die : All : Counts full PCIe requests before they're broken into a series of cache-line size requests as measured by DATA_REQ_OF_CPU and TXN_REQ_OF_CPU.", |
| "UMask": "0x1", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Num requests sent by PCIe - by target : Abort", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8E", |
| "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.ABORT", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0xFF", |
| "UMask": "0x80", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Num requests sent by PCIe - by target : Confined P2P", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8E", |
| "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.CONFINED_P2P", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0xFF", |
| "UMask": "0x40", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Num requests sent by PCIe - by target : Local P2P", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8E", |
| "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.LOC_P2P", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0xFF", |
| "UMask": "0x20", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Num requests sent by PCIe - by target : Multi-cast", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8E", |
| "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MCAST", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0xFF", |
| "UMask": "0x2", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Num requests sent by PCIe - by target : Memory", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8E", |
| "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MEM", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0xFF", |
| "UMask": "0x8", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Num requests sent by PCIe - by target : MsgB", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8E", |
| "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MSGB", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0xFF", |
| "UMask": "0x1", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Num requests sent by PCIe - by target : Remote P2P", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8E", |
| "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.REM_P2P", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0xFF", |
| "UMask": "0x10", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Num requests sent by PCIe - by target : Ubox", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8E", |
| "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.UBOX", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0xFF", |
| "UMask": "0x4", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "ITC address map 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8F", |
| "EventName": "UNC_IIO_NUM_TGT_MATCHED_REQ_OF_CPU", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Outbound cacheline requests issued : 64B requests issued to device", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xD0", |
| "EventName": "UNC_IIO_OUTBOUND_CL_REQS_ISSUED.TO_IO", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0xFF", |
| "PublicDescription": "Outbound cacheline requests issued : 64B requests issued to device : Each outbound cacheline granular request may need to make multiple passes through the pipeline. Each time a cacheline completes all its passes it advances line", |
| "UMask": "0x8", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Outbound TLP (transaction layer packet) requests issued : To device", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xD1", |
| "EventName": "UNC_IIO_OUTBOUND_TLP_REQS_ISSUED.TO_IO", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0xFF", |
| "PublicDescription": "Outbound TLP (transaction layer packet) requests issued : To device : Each time an outbound completes all its passes it advances the pointer", |
| "UMask": "0x8", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "PWT occupancy", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x42", |
| "EventName": "UNC_IIO_PWT_OCCUPANCY", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "PWT occupancy : Indicates how many page walks are outstanding at any point in time.", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "PCIe Request - cacheline complete : Passing data to be written", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x91", |
| "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.DATA", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0xFF", |
| "PublicDescription": "PCIe Request - cacheline complete : Passing data to be written : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes all its passes (e.g. finishes posting writes to all multi-cast targets) it advances line : Only for posted requests", |
| "UMask": "0x20", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "PCIe Request - cacheline complete : Issuing final read or write of line", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x91", |
| "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.FINAL_RD_WR", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0xFF", |
| "PublicDescription": "PCIe Request - cacheline complete : Issuing final read or write of line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes all its passes (e.g. finishes posting writes to all multi-cast targets) it advances line", |
| "UMask": "0x8", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "PCIe Request - cacheline complete : Request Ownership", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x91", |
| "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.REQ_OWN", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0xFF", |
| "PublicDescription": "PCIe Request - cacheline complete : Request Ownership : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes all its passes (e.g. finishes posting writes to all multi-cast targets) it advances line : Only for posted requests", |
| "UMask": "0x4", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "PCIe Request - cacheline complete : Writing line", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x91", |
| "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.WR", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0xFF", |
| "PublicDescription": "PCIe Request - cacheline complete : Writing line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes all its passes (e.g. finishes posting writes to all multi-cast targets) it advances line : Only for posted requests", |
| "UMask": "0x10", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "PCIe Request complete : Passing data to be written", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x92", |
| "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.DATA", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0xFF", |
| "PublicDescription": "PCIe Request complete : Passing data to be written : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a single PCIe request completes all its cacheline granular requests, it advances pointer. : Only for posted requests", |
| "UMask": "0x20", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "PCIe Request complete : Issuing final read or write of line", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x92", |
| "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.FINAL_RD_WR", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0xFF", |
| "PublicDescription": "PCIe Request complete : Issuing final read or write of line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a single PCIe request completes all its cacheline granular requests, it advances pointer.", |
| "UMask": "0x8", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "PCIe Request complete : Processing response from IOMMU", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x92", |
| "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.IOMMU_HIT", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0xFF", |
| "PublicDescription": "PCIe Request complete : Processing response from IOMMU : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a single PCIe request completes all its cacheline granular requests, it advances pointer.", |
| "UMask": "0x2", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "PCIe Request complete : Issuing to IOMMU", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x92", |
| "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.IOMMU_REQ", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0xFF", |
| "PublicDescription": "PCIe Request complete : Issuing to IOMMU : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a single PCIe request completes all its cacheline granular requests, it advances pointer.", |
| "UMask": "0x1", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "PCIe Request complete : Request Ownership", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x92", |
| "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.REQ_OWN", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0xFF", |
| "PublicDescription": "PCIe Request complete : Request Ownership : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a single PCIe request completes all its cacheline granular requests, it advances pointer. : Only for posted requests", |
| "UMask": "0x4", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "PCIe Request complete : Writing line", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x92", |
| "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.WR", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0xFF", |
| "PublicDescription": "PCIe Request complete : Writing line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a single PCIe request completes all its cacheline granular requests, it advances pointer. : Only for posted requests", |
| "UMask": "0x10", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "PCIe Request - pass complete : Passing data to be written", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x90", |
| "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.DATA", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0xFF", |
| "PublicDescription": "PCIe Request - pass complete : Passing data to be written : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes a single pass (e.g. posts a write to single multi-cast target) it advances state : Only for posted requests", |
| "UMask": "0x20", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "PCIe Request - pass complete : Issuing final read or write of line", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x90", |
| "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.FINAL_RD_WR", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0xFF", |
| "PublicDescription": "PCIe Request - pass complete : Issuing final read or write of line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes a single pass (e.g. posts a write to single multi-cast target) it advances state", |
| "UMask": "0x8", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "PCIe Request - pass complete : Request Ownership", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x90", |
| "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.REQ_OWN", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0xFF", |
| "PublicDescription": "PCIe Request - pass complete : Request Ownership : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes a single pass (e.g. posts a write to single multi-cast target) it advances state : Only for posted requests", |
| "UMask": "0x4", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "PCIe Request - pass complete : Writing line", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x90", |
| "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.WR", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0xFF", |
| "PublicDescription": "PCIe Request - pass complete : Writing line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes a single pass (e.g. posts a write to single multi-cast target) it advances state : Only for posted requests", |
| "UMask": "0x10", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Symbol Times on Link", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x82", |
| "EventName": "UNC_IIO_SYMBOL_TIMES", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Symbol Times on Link : Gen1 - increment once every 4nS, Gen2 - increment once every 2nS, Gen3 - increment once every 1nS", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xC1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.IOMMU0", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x100", |
| "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0", |
| "UMask": "0x40", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xC1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.IOMMU1", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x200", |
| "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1", |
| "UMask": "0x40", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xC1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART0", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x01", |
| "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", |
| "UMask": "0x40", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xC1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART1", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x02", |
| "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", |
| "UMask": "0x40", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xC1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART2", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x04", |
| "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", |
| "UMask": "0x40", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xC1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART3", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x08", |
| "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", |
| "UMask": "0x40", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xC1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART4", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x10", |
| "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", |
| "UMask": "0x40", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xC1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART5", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x20", |
| "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", |
| "UMask": "0x40", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xC1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART6", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x40", |
| "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", |
| "UMask": "0x40", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xC1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART7", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x80", |
| "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", |
| "UMask": "0x40", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xC1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.IOMMU0", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x100", |
| "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0", |
| "UMask": "0x10", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xC1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.IOMMU1", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x200", |
| "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1", |
| "UMask": "0x10", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xC1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART0", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x01", |
| "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", |
| "UMask": "0x10", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xC1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART1", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x02", |
| "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", |
| "UMask": "0x10", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xC1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART2", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x04", |
| "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", |
| "UMask": "0x10", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xC1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART3", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x08", |
| "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", |
| "UMask": "0x10", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xC1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART4", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x10", |
| "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", |
| "UMask": "0x10", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xC1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART5", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x20", |
| "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", |
| "UMask": "0x10", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xC1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART6", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x40", |
| "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", |
| "UMask": "0x10", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xC1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART7", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x80", |
| "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", |
| "UMask": "0x10", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xC1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.IOMMU0", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x100", |
| "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0", |
| "UMask": "0x80", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xC1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.IOMMU1", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x200", |
| "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1", |
| "UMask": "0x80", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xC1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART0", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x01", |
| "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", |
| "UMask": "0x80", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xC1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART1", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x02", |
| "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", |
| "UMask": "0x80", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xC1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART2", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x04", |
| "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", |
| "UMask": "0x80", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xC1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART3", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x08", |
| "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", |
| "UMask": "0x80", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xC1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART4", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x10", |
| "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", |
| "UMask": "0x80", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xC1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART5", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x20", |
| "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", |
| "UMask": "0x80", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xC1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART6", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x40", |
| "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", |
| "UMask": "0x80", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xC1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART7", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x80", |
| "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", |
| "UMask": "0x80", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xC1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.IOMMU0", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x100", |
| "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0", |
| "UMask": "0x20", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xC1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.IOMMU1", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x200", |
| "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1", |
| "UMask": "0x20", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xC1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART0", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x01", |
| "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", |
| "UMask": "0x20", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xC1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART1", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x02", |
| "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", |
| "UMask": "0x20", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xC1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART2", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x04", |
| "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", |
| "UMask": "0x20", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xC1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART3", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x08", |
| "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", |
| "UMask": "0x20", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xC1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART4", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x10", |
| "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", |
| "UMask": "0x20", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xC1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART5", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x20", |
| "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", |
| "UMask": "0x20", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xC1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART6", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x40", |
| "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", |
| "UMask": "0x20", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xC1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART7", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x80", |
| "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", |
| "UMask": "0x20", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xC1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.IOMMU0", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x100", |
| "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0", |
| "UMask": "0x4", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xC1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.IOMMU1", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x200", |
| "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1", |
| "UMask": "0x4", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xc1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x01", |
| "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", |
| "UMask": "0x4", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xc1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x02", |
| "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", |
| "UMask": "0x4", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xc1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x04", |
| "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", |
| "UMask": "0x4", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xc1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x08", |
| "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", |
| "UMask": "0x4", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xc1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART4", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x10", |
| "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", |
| "UMask": "0x4", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xc1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART5", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x20", |
| "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", |
| "UMask": "0x4", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xc1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART6", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x40", |
| "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", |
| "UMask": "0x4", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xc1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART7", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x80", |
| "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", |
| "UMask": "0x4", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xC1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.IOMMU0", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x100", |
| "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0", |
| "UMask": "0x1", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xC1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.IOMMU1", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x200", |
| "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1", |
| "UMask": "0x1", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xc1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x01", |
| "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", |
| "UMask": "0x1", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xc1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x02", |
| "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", |
| "UMask": "0x1", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xc1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x04", |
| "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", |
| "UMask": "0x1", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xc1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x08", |
| "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", |
| "UMask": "0x1", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xc1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART4", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x10", |
| "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", |
| "UMask": "0x1", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xc1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART5", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x20", |
| "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", |
| "UMask": "0x1", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xc1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART6", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x40", |
| "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", |
| "UMask": "0x1", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xc1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART7", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x80", |
| "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", |
| "UMask": "0x1", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xC1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.IOMMU0", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x100", |
| "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0", |
| "UMask": "0x8", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xC1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.IOMMU1", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x200", |
| "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1", |
| "UMask": "0x8", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xC1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART0", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x01", |
| "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", |
| "UMask": "0x8", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xC1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART1", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x02", |
| "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", |
| "UMask": "0x8", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xC1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART2", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x04", |
| "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", |
| "UMask": "0x8", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xC1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART3", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x08", |
| "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", |
| "UMask": "0x8", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xC1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART4", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x10", |
| "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", |
| "UMask": "0x8", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xC1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART5", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x20", |
| "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", |
| "UMask": "0x8", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xC1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART6", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x40", |
| "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", |
| "UMask": "0x8", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xC1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART7", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x80", |
| "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", |
| "UMask": "0x8", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xC1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.IOMMU0", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x200", |
| "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1", |
| "UMask": "0x2", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xC1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART0", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x01", |
| "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", |
| "UMask": "0x2", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xC1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART1", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x02", |
| "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", |
| "UMask": "0x2", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xC1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART2", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x04", |
| "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", |
| "UMask": "0x2", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xC1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART3", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x08", |
| "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", |
| "UMask": "0x2", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xC1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART4", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x10", |
| "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", |
| "UMask": "0x2", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xC1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART5", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x20", |
| "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", |
| "UMask": "0x2", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xC1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART6", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x40", |
| "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", |
| "UMask": "0x2", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xC1", |
| "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART7", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x80", |
| "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", |
| "UMask": "0x2", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.IOMMU0", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x100", |
| "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0", |
| "UMask": "0x10", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.IOMMU1", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x200", |
| "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1", |
| "UMask": "0x10", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART0", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x01", |
| "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", |
| "UMask": "0x10", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART1", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x02", |
| "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", |
| "UMask": "0x10", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART2", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x04", |
| "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", |
| "UMask": "0x10", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART3", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x08", |
| "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", |
| "UMask": "0x10", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART4", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x10", |
| "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", |
| "UMask": "0x10", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART5", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x20", |
| "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", |
| "UMask": "0x10", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART6", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x40", |
| "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", |
| "UMask": "0x10", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART7", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x80", |
| "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", |
| "UMask": "0x10", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.IOMMU0", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x100", |
| "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0", |
| "UMask": "0x80", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.IOMMU1", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x200", |
| "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1", |
| "UMask": "0x80", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART0", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x01", |
| "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", |
| "UMask": "0x80", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x02", |
| "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", |
| "UMask": "0x80", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART2", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x04", |
| "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", |
| "UMask": "0x80", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART3", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x08", |
| "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", |
| "UMask": "0x80", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART4", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x10", |
| "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", |
| "UMask": "0x80", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART5", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x20", |
| "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", |
| "UMask": "0x80", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART6", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x40", |
| "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", |
| "UMask": "0x80", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART7", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x80", |
| "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", |
| "UMask": "0x80", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.IOMMU0", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x100", |
| "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0", |
| "UMask": "0x4", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.IOMMU1", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x200", |
| "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1", |
| "UMask": "0x4", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x01", |
| "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", |
| "UMask": "0x4", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x02", |
| "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", |
| "UMask": "0x4", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x04", |
| "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", |
| "UMask": "0x4", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x08", |
| "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", |
| "UMask": "0x4", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART4", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x10", |
| "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", |
| "UMask": "0x4", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART5", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x20", |
| "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", |
| "UMask": "0x4", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART6", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x40", |
| "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", |
| "UMask": "0x4", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART7", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x80", |
| "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", |
| "UMask": "0x4", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.IOMMU0", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x100", |
| "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0", |
| "UMask": "0x1", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.IOMMU1", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x200", |
| "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1", |
| "UMask": "0x1", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x01", |
| "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", |
| "UMask": "0x1", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x02", |
| "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", |
| "UMask": "0x1", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x04", |
| "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", |
| "UMask": "0x1", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x08", |
| "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", |
| "UMask": "0x1", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART4", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x10", |
| "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", |
| "UMask": "0x1", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART5", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x20", |
| "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", |
| "UMask": "0x1", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART6", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x40", |
| "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", |
| "UMask": "0x1", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART7", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x80", |
| "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", |
| "UMask": "0x1", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested of the CPU : Messages", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.IOMMU0", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x100", |
| "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0", |
| "UMask": "0x40", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested of the CPU : Messages", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.IOMMU1", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x200", |
| "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1", |
| "UMask": "0x40", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested of the CPU : Messages", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART0", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x01", |
| "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", |
| "UMask": "0x40", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested of the CPU : Messages", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART1", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x02", |
| "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", |
| "UMask": "0x40", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested of the CPU : Messages", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART2", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x04", |
| "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", |
| "UMask": "0x40", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested of the CPU : Messages", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART3", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x08", |
| "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", |
| "UMask": "0x40", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested of the CPU : Messages", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART4", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x10", |
| "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", |
| "UMask": "0x40", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested of the CPU : Messages", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART5", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x20", |
| "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", |
| "UMask": "0x40", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested of the CPU : Messages", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART6", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x40", |
| "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", |
| "UMask": "0x40", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested of the CPU : Messages", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART7", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x80", |
| "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", |
| "UMask": "0x40", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.IOMMU0", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x100", |
| "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0", |
| "UMask": "0x8", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.IOMMU1", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x200", |
| "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1", |
| "UMask": "0x8", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART0", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x01", |
| "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", |
| "UMask": "0x8", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART1", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x02", |
| "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", |
| "UMask": "0x8", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART2", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x04", |
| "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", |
| "UMask": "0x8", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART3", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x08", |
| "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", |
| "UMask": "0x8", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART4", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x10", |
| "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", |
| "UMask": "0x8", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART5", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x20", |
| "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", |
| "UMask": "0x8", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART6", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x40", |
| "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", |
| "UMask": "0x8", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART7", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x80", |
| "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", |
| "UMask": "0x8", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.IOMMU0", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x100", |
| "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0", |
| "UMask": "0x2", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.IOMMU1", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x200", |
| "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1", |
| "UMask": "0x2", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART0", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x01", |
| "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", |
| "UMask": "0x2", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART1", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x02", |
| "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", |
| "UMask": "0x2", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART2", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x04", |
| "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", |
| "UMask": "0x2", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART3", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x08", |
| "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", |
| "UMask": "0x2", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART4", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x10", |
| "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", |
| "UMask": "0x2", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART5", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x20", |
| "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", |
| "UMask": "0x2", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART6", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x40", |
| "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", |
| "UMask": "0x2", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART7", |
| "Experimental": "1", |
| "FCMask": "0x07", |
| "PerPkg": "1", |
| "PortMask": "0x80", |
| "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", |
| "UMask": "0x2", |
| "Unit": "IIO" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x80", |
| "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x80", |
| "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x80", |
| "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR2", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x80", |
| "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR3", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", |
| "UMask": "0x8", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x80", |
| "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR4", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", |
| "UMask": "0x10", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x80", |
| "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR5", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", |
| "UMask": "0x20", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x80", |
| "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR6", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", |
| "UMask": "0x40", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x80", |
| "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR7", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", |
| "UMask": "0x80", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x81", |
| "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED1.TGR10", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x81", |
| "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED1.TGR8", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x81", |
| "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED1.TGR9", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x82", |
| "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x82", |
| "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x82", |
| "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR2", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x82", |
| "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR3", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", |
| "UMask": "0x8", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x82", |
| "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR4", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", |
| "UMask": "0x10", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x82", |
| "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR5", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", |
| "UMask": "0x20", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x82", |
| "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR6", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", |
| "UMask": "0x40", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x82", |
| "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR7", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", |
| "UMask": "0x80", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x83", |
| "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY1.TGR10", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x83", |
| "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY1.TGR8", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x83", |
| "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY1.TGR9", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x88", |
| "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x88", |
| "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x88", |
| "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR2", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x88", |
| "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR3", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", |
| "UMask": "0x8", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x88", |
| "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR4", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", |
| "UMask": "0x10", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x88", |
| "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR5", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", |
| "UMask": "0x20", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x88", |
| "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR6", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", |
| "UMask": "0x40", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x88", |
| "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR7", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", |
| "UMask": "0x80", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x89", |
| "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED1.TGR10", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x89", |
| "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED1.TGR8", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x89", |
| "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED1.TGR9", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8a", |
| "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8a", |
| "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8a", |
| "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR2", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8a", |
| "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR3", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", |
| "UMask": "0x8", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8a", |
| "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR4", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", |
| "UMask": "0x10", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8a", |
| "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR5", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", |
| "UMask": "0x20", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8a", |
| "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR6", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", |
| "UMask": "0x40", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8a", |
| "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR7", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", |
| "UMask": "0x80", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8b", |
| "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY1.TGR10", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8b", |
| "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY1.TGR8", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8b", |
| "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY1.TGR9", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR2", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR3", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", |
| "UMask": "0x8", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR4", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", |
| "UMask": "0x10", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR5", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", |
| "UMask": "0x20", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR6", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", |
| "UMask": "0x40", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x84", |
| "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR7", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", |
| "UMask": "0x80", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x85", |
| "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED1.TGR10", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x85", |
| "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED1.TGR8", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x85", |
| "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED1.TGR9", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x86", |
| "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x86", |
| "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x86", |
| "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR2", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x86", |
| "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR3", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", |
| "UMask": "0x8", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x86", |
| "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR4", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", |
| "UMask": "0x10", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x86", |
| "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR5", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", |
| "UMask": "0x20", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x86", |
| "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR6", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", |
| "UMask": "0x40", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x86", |
| "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR7", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", |
| "UMask": "0x80", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x87", |
| "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY1.TGR10", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x87", |
| "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY1.TGR8", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x87", |
| "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY1.TGR9", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8c", |
| "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8c", |
| "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8c", |
| "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR2", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8c", |
| "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR3", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", |
| "UMask": "0x8", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8c", |
| "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR4", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", |
| "UMask": "0x10", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8c", |
| "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR5", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", |
| "UMask": "0x20", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8c", |
| "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR6", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", |
| "UMask": "0x40", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8c", |
| "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR7", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", |
| "UMask": "0x80", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8d", |
| "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED1.TGR10", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8d", |
| "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED1.TGR8", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8d", |
| "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED1.TGR9", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8e", |
| "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8e", |
| "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8e", |
| "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR2", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8e", |
| "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR3", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", |
| "UMask": "0x8", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8e", |
| "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR4", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", |
| "UMask": "0x10", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8e", |
| "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR5", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", |
| "UMask": "0x20", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8e", |
| "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR6", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", |
| "UMask": "0x40", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8e", |
| "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR7", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", |
| "UMask": "0x80", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8f", |
| "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY1.TGR10", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8f", |
| "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY1.TGR8", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8f", |
| "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY1.TGR9", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Clockticks of the mesh to PCI (M2P)", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x01", |
| "EventName": "UNC_M2P_CLOCKTICKS", |
| "PerPkg": "1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Clockticks", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xc0", |
| "EventName": "UNC_M2P_CMS_CLOCKTICKS", |
| "PerPkg": "1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Distress signal asserted : DPT Local", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xaf", |
| "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_LOCAL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Distress signal asserted : DPT Local : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle triggered by this tile", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Distress signal asserted : DPT Remote", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xaf", |
| "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_NONLOCAL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Distress signal asserted : DPT Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle received by this tile", |
| "UMask": "0x8", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Distress signal asserted : DPT Stalled - IV", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xaf", |
| "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_STALL_IV", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Distress signal asserted : DPT Stalled - IV : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while regular IVs were received, causing DPT to be stalled", |
| "UMask": "0x40", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Distress signal asserted : DPT Stalled - No Credit", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xaf", |
| "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_STALL_NOCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Distress signal asserted : DPT Stalled - No Credit : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while credit not available causing DPT to be stalled", |
| "UMask": "0x80", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Distress signal asserted : Horizontal", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xaf", |
| "EventName": "UNC_M2P_DISTRESS_ASSERTED.HORZ", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Distress signal asserted : Horizontal : Counts the number of cycles either the local or incoming distress signals are asserted. : If TGR egress is full, then agents will throttle outgoing AD IDI transactions", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Distress signal asserted : Vertical", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xaf", |
| "EventName": "UNC_M2P_DISTRESS_ASSERTED.VERT", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Distress signal asserted : Vertical : Counts the number of cycles either the local or incoming distress signals are asserted. : If IRQ egress is full, then agents will throttle outgoing AD IDI transactions", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Egress Blocking due to Ordering requirements : Down", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xba", |
| "EventName": "UNC_M2P_EGRESS_ORDERING.IV_SNOOPGO_DN", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Egress Blocking due to Ordering requirements : Down : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Egress Blocking due to Ordering requirements : Up", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xba", |
| "EventName": "UNC_M2P_EGRESS_ORDERING.IV_SNOOPGO_UP", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Egress Blocking due to Ordering requirements : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Horizontal AD Ring In Use : Left and Even", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xb6", |
| "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.LEFT_EVEN", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Horizontal AD Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Horizontal AD Ring In Use : Left and Odd", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xb6", |
| "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.LEFT_ODD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Horizontal AD Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Horizontal AD Ring In Use : Right and Even", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xb6", |
| "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.RIGHT_EVEN", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Horizontal AD Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Horizontal AD Ring In Use : Right and Odd", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xb6", |
| "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.RIGHT_ODD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Horizontal AD Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x8", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Horizontal AK Ring In Use : Left and Even", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xbb", |
| "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.LEFT_EVEN", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xbb", |
| "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.LEFT_ODD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Horizontal AK Ring In Use : Right and Even", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xbb", |
| "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.RIGHT_EVEN", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xbb", |
| "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.RIGHT_ODD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x8", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Horizontal AK Ring In Use : Left and Even", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xb7", |
| "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.LEFT_EVEN", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xb7", |
| "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.LEFT_ODD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Horizontal AK Ring In Use : Right and Even", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xb7", |
| "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.RIGHT_EVEN", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xb7", |
| "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.RIGHT_ODD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x8", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Horizontal BL Ring in Use : Left and Even", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xb8", |
| "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.LEFT_EVEN", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Horizontal BL Ring in Use : Left and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Horizontal BL Ring in Use : Left and Odd", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xb8", |
| "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.LEFT_ODD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Horizontal BL Ring in Use : Left and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Horizontal BL Ring in Use : Right and Even", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xb8", |
| "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.RIGHT_EVEN", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Horizontal BL Ring in Use : Right and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Horizontal BL Ring in Use : Right and Odd", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xb8", |
| "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.RIGHT_ODD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Horizontal BL Ring in Use : Right and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x8", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Horizontal IV Ring in Use : Left", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xb9", |
| "EventName": "UNC_M2P_HORZ_RING_IV_IN_USE.LEFT", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Horizontal IV Ring in Use : Left : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Horizontal IV Ring in Use : Right", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xb9", |
| "EventName": "UNC_M2P_HORZ_RING_IV_IN_USE.RIGHT", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Horizontal IV Ring in Use : Right : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "M2PCIe IIO Credit Acquired : DRS", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x33", |
| "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.DRS_0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "M2PCIe IIO Credit Acquired : DRS : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS message class.", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "M2PCIe IIO Credit Acquired : DRS", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x33", |
| "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.DRS_1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "M2PCIe IIO Credit Acquired : DRS : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS message class.", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "M2PCIe IIO Credit Acquired : NCB", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x33", |
| "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCB_0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "M2PCIe IIO Credit Acquired : NCB : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB message class.", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "M2PCIe IIO Credit Acquired : NCB", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x33", |
| "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCB_1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "M2PCIe IIO Credit Acquired : NCB : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB message class.", |
| "UMask": "0x8", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "M2PCIe IIO Credit Acquired : NCS", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x33", |
| "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCS_0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "M2PCIe IIO Credit Acquired : NCS : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCS message class.", |
| "UMask": "0x10", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "M2PCIe IIO Credit Acquired : NCS", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x33", |
| "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCS_1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "M2PCIe IIO Credit Acquired : NCS : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credit for transfer through CMS Port 0s to the IIO for the NCS message class.", |
| "UMask": "0x20", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : DRS", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x34", |
| "EventName": "UNC_M2P_IIO_CREDITS_REJECT.DRS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "M2PCIe IIO Failed to Acquire a Credit : DRS : Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits to the IIO for the DRS message class.", |
| "UMask": "0x8", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : NCB", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x34", |
| "EventName": "UNC_M2P_IIO_CREDITS_REJECT.NCB", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "M2PCIe IIO Failed to Acquire a Credit : NCB : Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits to the IIO for the NCB message class.", |
| "UMask": "0x10", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : NCS", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x34", |
| "EventName": "UNC_M2P_IIO_CREDITS_REJECT.NCS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "M2PCIe IIO Failed to Acquire a Credit : NCS : Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits to the IIO for the NCS message class.", |
| "UMask": "0x20", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x32", |
| "EventName": "UNC_M2P_IIO_CREDITS_USED.DRS_0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 0 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS message class.", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x32", |
| "EventName": "UNC_M2P_IIO_CREDITS_USED.DRS_1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 1 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS message class.", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x32", |
| "EventName": "UNC_M2P_IIO_CREDITS_USED.NCB_0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 0 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB message class.", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x32", |
| "EventName": "UNC_M2P_IIO_CREDITS_USED.NCB_1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 1 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB message class.", |
| "UMask": "0x8", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x32", |
| "EventName": "UNC_M2P_IIO_CREDITS_USED.NCS_0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 0 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCS message class.", |
| "UMask": "0x10", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x32", |
| "EventName": "UNC_M2P_IIO_CREDITS_USED.NCS_1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 1 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credit for transfer through CMS Port 0s to the IIO for the NCS message class.", |
| "UMask": "0x20", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF0 - NCB", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x46", |
| "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF0_NCB", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF0 - NCS", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x46", |
| "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF0_NCS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF1 - NCB", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x46", |
| "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF1_NCB", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF1 - NCS", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x46", |
| "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF1_NCS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x8", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF2 - NCB", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x46", |
| "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF2_NCB", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x10", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF2 - NCS", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x46", |
| "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF2_NCS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x20", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF3 - NCB", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x46", |
| "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF3_NCB", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x40", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF3 - NCS", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x46", |
| "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF3_NCS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x80", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF4 - NCB", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x47", |
| "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF4_NCB", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF4 - NCS", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x47", |
| "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF4_NCS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF5 - NCB", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x47", |
| "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF5_NCB", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF5 - NCS", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x47", |
| "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF5_NCS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x8", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF0 - NCB", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x19", |
| "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF0_NCB", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF0 - NCS", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x19", |
| "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF0_NCS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF1 - NCB", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x19", |
| "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF1_NCB", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF1 - NCS", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x19", |
| "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF1_NCS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x8", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF2 - NCB", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x19", |
| "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF2_NCB", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x10", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF2 - NCS", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x19", |
| "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF2_NCS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x20", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF3 - NCB", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x19", |
| "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF3_NCB", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x10", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF3 - NCS", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x19", |
| "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF3_NCS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x20", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF4 - NCB", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x1a", |
| "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF4_NCB", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF4 - NCS", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x1a", |
| "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF4_NCS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF5 - NCB", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x1a", |
| "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF5_NCB", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF5 - NCS", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x1a", |
| "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF5_NCS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x8", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Local P2P Shared Credits Returned : Agent0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x17", |
| "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Local P2P Shared Credits Returned : Agent1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x17", |
| "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Local P2P Shared Credits Returned : Agent2", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x17", |
| "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_2", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x44", |
| "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x44", |
| "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent2", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x44", |
| "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_2", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent3", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x44", |
| "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_3", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x8", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent4", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x44", |
| "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_4", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x10", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent5", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x44", |
| "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_5", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x20", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF0 - NCB", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x40", |
| "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF0_NCB", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF0 - NCS", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x40", |
| "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF0_NCS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF1 - NCB", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x40", |
| "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF1_NCB", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF1 - NCS", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x40", |
| "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF1_NCS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x8", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF2 - NCB", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x40", |
| "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF2_NCB", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x10", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF2 - NCS", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x40", |
| "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF2_NCS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x20", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF3 - NCB", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x40", |
| "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF3_NCB", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x40", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF3 - NCS", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x40", |
| "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF3_NCS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x80", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF4 - NCB", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x41", |
| "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF4_NCB", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF4 - NCS", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x41", |
| "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF4_NCS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF5 - NCB", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x41", |
| "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF5_NCB", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF5 - NCS", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x41", |
| "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF5_NCS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x8", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF0 - NCB", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x4a", |
| "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF0_NCB", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF0 - NCS", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x4a", |
| "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF0_NCS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF1 - NCB", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x4a", |
| "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF1_NCB", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF1 - NCS", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x4a", |
| "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF1_NCS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x8", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF2 - NCB", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x4a", |
| "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF2_NCB", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x10", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF2 - NCS", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x4a", |
| "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF2_NCS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x20", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF3 - NCB", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x4a", |
| "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF3_NCB", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x40", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF3 - NCS", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x4a", |
| "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF3_NCS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x80", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF4 - NCB", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x4b", |
| "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF4_NCB", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF4 - NCS", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x4b", |
| "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF4_NCS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF5 - NCB", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x4b", |
| "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF5_NCB", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF5 - NCS", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x4b", |
| "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF5_NCS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x8", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xe6", |
| "EventName": "UNC_M2P_MISC_EXTERNAL.MBE_INST0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xe6", |
| "EventName": "UNC_M2P_MISC_EXTERNAL.MBE_INST1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "P2P Credit Occupancy : All", |
| "Counter": "0,1", |
| "EventCode": "0x14", |
| "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.ALL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x10", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "P2P Credit Occupancy : Local NCB", |
| "Counter": "0,1", |
| "EventCode": "0x14", |
| "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.LOCAL_NCB", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "P2P Credit Occupancy : Local NCS", |
| "Counter": "0,1", |
| "EventCode": "0x14", |
| "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.LOCAL_NCS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "P2P Credit Occupancy : Remote NCB", |
| "Counter": "0,1", |
| "EventCode": "0x14", |
| "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.REMOTE_NCB", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "P2P Credit Occupancy : Remote NCS", |
| "Counter": "0,1", |
| "EventCode": "0x14", |
| "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.REMOTE_NCS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x8", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Dedicated Credits Received : All", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x16", |
| "EventName": "UNC_M2P_P2P_DED_RECEIVED.ALL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x10", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Dedicated Credits Received : Local NCB", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x16", |
| "EventName": "UNC_M2P_P2P_DED_RECEIVED.LOCAL_NCB", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Dedicated Credits Received : Local NCS", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x16", |
| "EventName": "UNC_M2P_P2P_DED_RECEIVED.LOCAL_NCS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Dedicated Credits Received : Remote NCB", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x16", |
| "EventName": "UNC_M2P_P2P_DED_RECEIVED.REMOTE_NCB", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Dedicated Credits Received : Remote NCS", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x16", |
| "EventName": "UNC_M2P_P2P_DED_RECEIVED.REMOTE_NCS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x8", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Shared Credits Received : All", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x15", |
| "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.ALL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x10", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Shared Credits Received : Local NCB", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x15", |
| "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.LOCAL_NCB", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Shared Credits Received : Local NCS", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x15", |
| "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.LOCAL_NCS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Shared Credits Received : Remote NCB", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x15", |
| "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.REMOTE_NCB", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Shared Credits Received : Remote NCS", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x15", |
| "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.REMOTE_NCS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x8", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Remote P2P Shared Credits Returned : Agent0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x18", |
| "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Remote P2P Shared Credits Returned : Agent1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x18", |
| "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Remote P2P Shared Credits Returned : Agent2", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x18", |
| "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_2", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Remote Shared P2P Credit Returned to credit ring : Agent0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x45", |
| "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Remote Shared P2P Credit Returned to credit ring : Agent1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x45", |
| "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Remote Shared P2P Credit Returned to credit ring : Agent2", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x45", |
| "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_2", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Messages that bounced on the Horizontal Ring. : AD", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xac", |
| "EventName": "UNC_M2P_RING_BOUNCES_HORZ.AD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Messages that bounced on the Horizontal Ring. : AD : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Messages that bounced on the Horizontal Ring. : AK", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xac", |
| "EventName": "UNC_M2P_RING_BOUNCES_HORZ.AK", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Messages that bounced on the Horizontal Ring. : AK : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Messages that bounced on the Horizontal Ring. : BL", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xac", |
| "EventName": "UNC_M2P_RING_BOUNCES_HORZ.BL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Messages that bounced on the Horizontal Ring. : BL : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Messages that bounced on the Horizontal Ring. : IV", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xac", |
| "EventName": "UNC_M2P_RING_BOUNCES_HORZ.IV", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Messages that bounced on the Horizontal Ring. : IV : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", |
| "UMask": "0x8", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Messages that bounced on the Vertical Ring. : AD", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xaa", |
| "EventName": "UNC_M2P_RING_BOUNCES_VERT.AD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Messages that bounced on the Vertical Ring. : AD : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xaa", |
| "EventName": "UNC_M2P_RING_BOUNCES_VERT.AK", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Messages that bounced on the Vertical Ring.", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xaa", |
| "EventName": "UNC_M2P_RING_BOUNCES_VERT.AKC", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Messages that bounced on the Vertical Ring. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", |
| "UMask": "0x10", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xaa", |
| "EventName": "UNC_M2P_RING_BOUNCES_VERT.BL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache.", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xaa", |
| "EventName": "UNC_M2P_RING_BOUNCES_VERT.IV", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", |
| "UMask": "0x8", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Sink Starvation on Horizontal Ring : AD", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xad", |
| "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.AD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Sink Starvation on Horizontal Ring : AK", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xad", |
| "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.AK", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xad", |
| "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.AK_AG1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x20", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Sink Starvation on Horizontal Ring : BL", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xad", |
| "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.BL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Sink Starvation on Horizontal Ring : IV", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xad", |
| "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.IV", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x8", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Sink Starvation on Vertical Ring : AD", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xab", |
| "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.AD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Sink Starvation on Vertical Ring : Acknowledgements to core", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xab", |
| "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.AK", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Sink Starvation on Vertical Ring", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xab", |
| "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.AKC", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x10", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Sink Starvation on Vertical Ring : Data Responses to core", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xab", |
| "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.BL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of processor's cache.", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xab", |
| "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.IV", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x8", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Source Throttle", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xae", |
| "EventName": "UNC_M2P_RING_SRC_THRTL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x10", |
| "EventName": "UNC_M2P_RxC_CYCLES_NE.ALL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.", |
| "UMask": "0x80", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x10", |
| "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_IDI", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x10", |
| "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_NCB", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x10", |
| "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_NCS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x10", |
| "EventName": "UNC_M2P_RxC_CYCLES_NE.IIO_NCB", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.", |
| "UMask": "0x20", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x10", |
| "EventName": "UNC_M2P_RxC_CYCLES_NE.IIO_NCS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.", |
| "UMask": "0x40", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Ingress (from CMS) Queue Inserts", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x11", |
| "EventName": "UNC_M2P_RxC_INSERTS.ALL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.", |
| "UMask": "0x80", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Ingress (from CMS) Queue Inserts", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x11", |
| "EventName": "UNC_M2P_RxC_INSERTS.CHA_IDI", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Ingress (from CMS) Queue Inserts", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x11", |
| "EventName": "UNC_M2P_RxC_INSERTS.CHA_NCB", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Ingress (from CMS) Queue Inserts", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x11", |
| "EventName": "UNC_M2P_RxC_INSERTS.CHA_NCS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Ingress (from CMS) Queue Inserts", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x11", |
| "EventName": "UNC_M2P_RxC_INSERTS.IIO_NCB", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.", |
| "UMask": "0x20", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Ingress (from CMS) Queue Inserts", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x11", |
| "EventName": "UNC_M2P_RxC_INSERTS.IIO_NCS", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.", |
| "UMask": "0x40", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Transgress Injection Starvation : AD - All", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xe5", |
| "EventName": "UNC_M2P_RxR_BUSY_STARVED.AD_ALL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited", |
| "UMask": "0x11", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Transgress Injection Starvation : AD - Credited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xe5", |
| "EventName": "UNC_M2P_RxR_BUSY_STARVED.AD_CRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", |
| "UMask": "0x10", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Transgress Injection Starvation : AD - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xe5", |
| "EventName": "UNC_M2P_RxR_BUSY_STARVED.AD_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Transgress Injection Starvation : BL - All", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xe5", |
| "EventName": "UNC_M2P_RxR_BUSY_STARVED.BL_ALL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited", |
| "UMask": "0x44", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Transgress Injection Starvation : BL - Credited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xe5", |
| "EventName": "UNC_M2P_RxR_BUSY_STARVED.BL_CRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", |
| "UMask": "0x40", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Transgress Injection Starvation : BL - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xe5", |
| "EventName": "UNC_M2P_RxR_BUSY_STARVED.BL_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Transgress Ingress Bypass : AD - All", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xe2", |
| "EventName": "UNC_M2P_RxR_BYPASS.AD_ALL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Ingress Bypass : AD - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited", |
| "UMask": "0x11", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Transgress Ingress Bypass : AD - Credited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xe2", |
| "EventName": "UNC_M2P_RxR_BYPASS.AD_CRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Ingress Bypass : AD - Credited : Number of packets bypassing the CMS Ingress", |
| "UMask": "0x10", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Transgress Ingress Bypass : AD - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xe2", |
| "EventName": "UNC_M2P_RxR_BYPASS.AD_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Ingress Bypass : AD - Uncredited : Number of packets bypassing the CMS Ingress", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Transgress Ingress Bypass : AK", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xe2", |
| "EventName": "UNC_M2P_RxR_BYPASS.AK", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Ingress Bypass : AK : Number of packets bypassing the CMS Ingress", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xe2", |
| "EventName": "UNC_M2P_RxR_BYPASS.AKC_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Ingress Bypass : AKC - Uncredited : Number of packets bypassing the CMS Ingress", |
| "UMask": "0x80", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Transgress Ingress Bypass : BL - All", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xe2", |
| "EventName": "UNC_M2P_RxR_BYPASS.BL_ALL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Ingress Bypass : BL - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited", |
| "UMask": "0x44", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Transgress Ingress Bypass : BL - Credited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xe2", |
| "EventName": "UNC_M2P_RxR_BYPASS.BL_CRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Ingress Bypass : BL - Credited : Number of packets bypassing the CMS Ingress", |
| "UMask": "0x40", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xe2", |
| "EventName": "UNC_M2P_RxR_BYPASS.BL_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Ingress Bypass : BL - Uncredited : Number of packets bypassing the CMS Ingress", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Transgress Ingress Bypass : IV", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xe2", |
| "EventName": "UNC_M2P_RxR_BYPASS.IV", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Ingress Bypass : IV : Number of packets bypassing the CMS Ingress", |
| "UMask": "0x8", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Transgress Injection Starvation : AD - All", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xe3", |
| "EventName": "UNC_M2P_RxR_CRD_STARVED.AD_ALL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited", |
| "UMask": "0x11", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Transgress Injection Starvation : AD - Credited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xe3", |
| "EventName": "UNC_M2P_RxR_CRD_STARVED.AD_CRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", |
| "UMask": "0x10", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Transgress Injection Starvation : AD - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xe3", |
| "EventName": "UNC_M2P_RxR_CRD_STARVED.AD_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Transgress Injection Starvation : AK", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xe3", |
| "EventName": "UNC_M2P_RxR_CRD_STARVED.AK", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Injection Starvation : AK : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Transgress Injection Starvation : BL - All", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xe3", |
| "EventName": "UNC_M2P_RxR_CRD_STARVED.BL_ALL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited", |
| "UMask": "0x44", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Transgress Injection Starvation : BL - Credited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xe3", |
| "EventName": "UNC_M2P_RxR_CRD_STARVED.BL_CRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", |
| "UMask": "0x40", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Transgress Injection Starvation : BL - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xe3", |
| "EventName": "UNC_M2P_RxR_CRD_STARVED.BL_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Transgress Injection Starvation : IFV - Credited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xe3", |
| "EventName": "UNC_M2P_RxR_CRD_STARVED.IFV", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Injection Starvation : IFV - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", |
| "UMask": "0x80", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Transgress Injection Starvation : IV", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xe3", |
| "EventName": "UNC_M2P_RxR_CRD_STARVED.IV", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Injection Starvation : IV : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", |
| "UMask": "0x8", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Transgress Injection Starvation", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xe4", |
| "EventName": "UNC_M2P_RxR_CRD_STARVED_1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Injection Starvation : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Transgress Ingress Allocations : AD - All", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xe1", |
| "EventName": "UNC_M2P_RxR_INSERTS.AD_ALL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Ingress Allocations : AD - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited", |
| "UMask": "0x11", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Transgress Ingress Allocations : AD - Credited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xe1", |
| "EventName": "UNC_M2P_RxR_INSERTS.AD_CRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Ingress Allocations : AD - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", |
| "UMask": "0x10", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Transgress Ingress Allocations : AD - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xe1", |
| "EventName": "UNC_M2P_RxR_INSERTS.AD_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Ingress Allocations : AD - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Transgress Ingress Allocations : AK", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xe1", |
| "EventName": "UNC_M2P_RxR_INSERTS.AK", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Ingress Allocations : AK : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Transgress Ingress Allocations : AKC - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xe1", |
| "EventName": "UNC_M2P_RxR_INSERTS.AKC_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Ingress Allocations : AKC - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", |
| "UMask": "0x80", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Transgress Ingress Allocations : BL - All", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xe1", |
| "EventName": "UNC_M2P_RxR_INSERTS.BL_ALL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Ingress Allocations : BL - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited", |
| "UMask": "0x44", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Transgress Ingress Allocations : BL - Credited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xe1", |
| "EventName": "UNC_M2P_RxR_INSERTS.BL_CRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Ingress Allocations : BL - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", |
| "UMask": "0x40", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Transgress Ingress Allocations : BL - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xe1", |
| "EventName": "UNC_M2P_RxR_INSERTS.BL_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Ingress Allocations : BL - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Transgress Ingress Allocations : IV", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xe1", |
| "EventName": "UNC_M2P_RxR_INSERTS.IV", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Ingress Allocations : IV : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", |
| "UMask": "0x8", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Transgress Ingress Occupancy : AD - All", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xe0", |
| "EventName": "UNC_M2P_RxR_OCCUPANCY.AD_ALL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Ingress Occupancy : AD - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited", |
| "UMask": "0x11", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Transgress Ingress Occupancy : AD - Credited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xe0", |
| "EventName": "UNC_M2P_RxR_OCCUPANCY.AD_CRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Ingress Occupancy : AD - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", |
| "UMask": "0x10", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Transgress Ingress Occupancy : AD - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xe0", |
| "EventName": "UNC_M2P_RxR_OCCUPANCY.AD_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Ingress Occupancy : AD - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Transgress Ingress Occupancy : AK", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xe0", |
| "EventName": "UNC_M2P_RxR_OCCUPANCY.AK", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Ingress Occupancy : AK : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xe0", |
| "EventName": "UNC_M2P_RxR_OCCUPANCY.AKC_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Ingress Occupancy : AKC - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", |
| "UMask": "0x80", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Transgress Ingress Occupancy : BL - All", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xe0", |
| "EventName": "UNC_M2P_RxR_OCCUPANCY.BL_ALL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Ingress Occupancy : BL - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited", |
| "UMask": "0x44", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Transgress Ingress Occupancy : BL - Credited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xe0", |
| "EventName": "UNC_M2P_RxR_OCCUPANCY.BL_CRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Ingress Occupancy : BL - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", |
| "UMask": "0x20", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xe0", |
| "EventName": "UNC_M2P_RxR_OCCUPANCY.BL_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Ingress Occupancy : BL - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Transgress Ingress Occupancy : IV", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xe0", |
| "EventName": "UNC_M2P_RxR_OCCUPANCY.IV", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Transgress Ingress Occupancy : IV : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", |
| "UMask": "0x8", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xd0", |
| "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xd0", |
| "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xd0", |
| "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR2", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xd0", |
| "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR3", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x8", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xd0", |
| "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR4", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x10", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xd0", |
| "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR5", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x20", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xd0", |
| "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR6", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x40", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xd0", |
| "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR7", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x80", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xd2", |
| "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xd2", |
| "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xd2", |
| "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR2", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xd2", |
| "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR3", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x8", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xd2", |
| "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR4", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x10", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xd2", |
| "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR5", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x20", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xd2", |
| "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR6", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x40", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xd2", |
| "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR7", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x80", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xd4", |
| "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xd4", |
| "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xd4", |
| "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR2", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xd4", |
| "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR3", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x8", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xd4", |
| "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR4", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x10", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xd4", |
| "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR5", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x20", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xd4", |
| "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x40", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xd4", |
| "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x80", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xd6", |
| "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xd6", |
| "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xd6", |
| "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xd6", |
| "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x8", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xd6", |
| "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x10", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xd6", |
| "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x20", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xd6", |
| "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x40", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xd6", |
| "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x80", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xd1", |
| "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xd1", |
| "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xd1", |
| "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xd3", |
| "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xd3", |
| "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xd3", |
| "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xd5", |
| "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xd5", |
| "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xd5", |
| "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xd7", |
| "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xd7", |
| "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xd7", |
| "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "UNC_M2P_TxC_CREDITS.PRQ", |
| "Counter": "0,1", |
| "EventCode": "0x2d", |
| "EventName": "UNC_M2P_TxC_CREDITS.PRQ", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Egress (to CMS) Cycles Full", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x25", |
| "EventName": "UNC_M2P_TxC_CYCLES_FULL.AD_0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Egress (to CMS) Cycles Full", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x25", |
| "EventName": "UNC_M2P_TxC_CYCLES_FULL.AD_1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.", |
| "UMask": "0x10", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Egress (to CMS) Cycles Full", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x25", |
| "EventName": "UNC_M2P_TxC_CYCLES_FULL.AK_0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Egress (to CMS) Cycles Full", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x25", |
| "EventName": "UNC_M2P_TxC_CYCLES_FULL.AK_1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.", |
| "UMask": "0x20", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Egress (to CMS) Cycles Full", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x25", |
| "EventName": "UNC_M2P_TxC_CYCLES_FULL.BL_0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Egress (to CMS) Cycles Full", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x25", |
| "EventName": "UNC_M2P_TxC_CYCLES_FULL.BL_1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.", |
| "UMask": "0x40", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Egress (to CMS) Cycles Not Empty", |
| "Counter": "0,1", |
| "EventCode": "0x23", |
| "EventName": "UNC_M2P_TxC_CYCLES_NE.AD_0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters.", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Egress (to CMS) Cycles Not Empty", |
| "Counter": "0,1", |
| "EventCode": "0x23", |
| "EventName": "UNC_M2P_TxC_CYCLES_NE.AD_1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters.", |
| "UMask": "0x10", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Egress (to CMS) Cycles Not Empty", |
| "Counter": "0,1", |
| "EventCode": "0x23", |
| "EventName": "UNC_M2P_TxC_CYCLES_NE.AK_0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters.", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Egress (to CMS) Cycles Not Empty", |
| "Counter": "0,1", |
| "EventCode": "0x23", |
| "EventName": "UNC_M2P_TxC_CYCLES_NE.AK_1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters.", |
| "UMask": "0x20", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Egress (to CMS) Cycles Not Empty", |
| "Counter": "0,1", |
| "EventCode": "0x23", |
| "EventName": "UNC_M2P_TxC_CYCLES_NE.BL_0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters.", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Egress (to CMS) Cycles Not Empty", |
| "Counter": "0,1", |
| "EventCode": "0x23", |
| "EventName": "UNC_M2P_TxC_CYCLES_NE.BL_1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters.", |
| "UMask": "0x40", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Egress (to CMS) Ingress", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x24", |
| "EventName": "UNC_M2P_TxC_INSERTS.AD_0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Egress (to CMS) Ingress : Counts the number of number of messages inserted into the the M2PCIe Egress queue. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Egress (to CMS) Ingress", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x24", |
| "EventName": "UNC_M2P_TxC_INSERTS.AD_1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Egress (to CMS) Ingress : Counts the number of number of messages inserted into the the M2PCIe Egress queue. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.", |
| "UMask": "0x10", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Egress (to CMS) Ingress", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x24", |
| "EventName": "UNC_M2P_TxC_INSERTS.AK_CRD_0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Egress (to CMS) Ingress : Counts the number of number of messages inserted into the the M2PCIe Egress queue. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.", |
| "UMask": "0x8", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Egress (to CMS) Ingress", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x24", |
| "EventName": "UNC_M2P_TxC_INSERTS.AK_CRD_1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Egress (to CMS) Ingress : Counts the number of number of messages inserted into the the M2PCIe Egress queue. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.", |
| "UMask": "0x80", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Egress (to CMS) Ingress", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x24", |
| "EventName": "UNC_M2P_TxC_INSERTS.BL_0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Egress (to CMS) Ingress : Counts the number of number of messages inserted into the the M2PCIe Egress queue. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Egress (to CMS) Ingress", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x24", |
| "EventName": "UNC_M2P_TxC_INSERTS.BL_1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Egress (to CMS) Ingress : Counts the number of number of messages inserted into the the M2PCIe Egress queue. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.", |
| "UMask": "0x40", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal ADS Used : AD - All", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xa6", |
| "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.AD_ALL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal ADS Used : AD - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited", |
| "UMask": "0x11", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal ADS Used : AD - Credited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xa6", |
| "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.AD_CRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal ADS Used : AD - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", |
| "UMask": "0x10", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xa6", |
| "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.AD_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal ADS Used : AD - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal ADS Used : BL - All", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xa6", |
| "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.BL_ALL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal ADS Used : BL - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited", |
| "UMask": "0x44", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal ADS Used : BL - Credited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xa6", |
| "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.BL_CRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal ADS Used : BL - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", |
| "UMask": "0x40", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xa6", |
| "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.BL_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal ADS Used : BL - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Bypass Used : AD - All", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xa7", |
| "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AD_ALL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Bypass Used : AD - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited", |
| "UMask": "0x11", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xa7", |
| "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AD_CRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Bypass Used : AD - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", |
| "UMask": "0x10", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Bypass Used : AD - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xa7", |
| "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AD_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Bypass Used : AD - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Bypass Used : AK", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xa7", |
| "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AK", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Bypass Used : AK : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xa7", |
| "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AKC_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Bypass Used : AKC - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", |
| "UMask": "0x80", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Bypass Used : BL - All", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xa7", |
| "EventName": "UNC_M2P_TxR_HORZ_BYPASS.BL_ALL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Bypass Used : BL - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited", |
| "UMask": "0x44", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xa7", |
| "EventName": "UNC_M2P_TxR_HORZ_BYPASS.BL_CRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Bypass Used : BL - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", |
| "UMask": "0x40", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xa7", |
| "EventName": "UNC_M2P_TxR_HORZ_BYPASS.BL_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Bypass Used : BL - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Bypass Used : IV", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xa7", |
| "EventName": "UNC_M2P_TxR_HORZ_BYPASS.IV", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Bypass Used : IV : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", |
| "UMask": "0x8", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xa2", |
| "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AD_ALL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", |
| "UMask": "0x11", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xa2", |
| "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AD_CRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", |
| "UMask": "0x10", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xa2", |
| "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AD_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AK", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xa2", |
| "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AK", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AK : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xa2", |
| "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AKC_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", |
| "UMask": "0x80", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xa2", |
| "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.BL_ALL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", |
| "UMask": "0x44", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xa2", |
| "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.BL_CRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", |
| "UMask": "0x40", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xa2", |
| "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.BL_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : IV", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xa2", |
| "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.IV", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : IV : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", |
| "UMask": "0x8", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xa3", |
| "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AD_ALL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", |
| "UMask": "0x11", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xa3", |
| "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AD_CRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", |
| "UMask": "0x10", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xa3", |
| "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AD_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xa3", |
| "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AK", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xa3", |
| "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AKC_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", |
| "UMask": "0x80", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xa3", |
| "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.BL_ALL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", |
| "UMask": "0x44", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xa3", |
| "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.BL_CRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", |
| "UMask": "0x40", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xa3", |
| "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.BL_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xa3", |
| "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.IV", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", |
| "UMask": "0x8", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Egress Inserts : AD - All", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xa1", |
| "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AD_ALL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Egress Inserts : AD - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", |
| "UMask": "0x11", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xa1", |
| "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AD_CRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Egress Inserts : AD - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", |
| "UMask": "0x10", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Egress Inserts : AD - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xa1", |
| "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AD_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Egress Inserts : AD - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Egress Inserts : AK", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xa1", |
| "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AK", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Egress Inserts : AK : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xa1", |
| "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AKC_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", |
| "UMask": "0x80", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Egress Inserts : BL - All", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xa1", |
| "EventName": "UNC_M2P_TxR_HORZ_INSERTS.BL_ALL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Egress Inserts : BL - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", |
| "UMask": "0x44", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xa1", |
| "EventName": "UNC_M2P_TxR_HORZ_INSERTS.BL_CRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Egress Inserts : BL - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", |
| "UMask": "0x40", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xa1", |
| "EventName": "UNC_M2P_TxR_HORZ_INSERTS.BL_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Egress Inserts : BL - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Egress Inserts : IV", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xa1", |
| "EventName": "UNC_M2P_TxR_HORZ_INSERTS.IV", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Egress Inserts : IV : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", |
| "UMask": "0x8", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Egress NACKs : AD - All", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xa4", |
| "EventName": "UNC_M2P_TxR_HORZ_NACK.AD_ALL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Egress NACKs : AD - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited", |
| "UMask": "0x11", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xa4", |
| "EventName": "UNC_M2P_TxR_HORZ_NACK.AD_CRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Egress NACKs : AD - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", |
| "UMask": "0x10", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Egress NACKs : AD - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xa4", |
| "EventName": "UNC_M2P_TxR_HORZ_NACK.AD_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Egress NACKs : AD - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Egress NACKs : AK", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xa4", |
| "EventName": "UNC_M2P_TxR_HORZ_NACK.AK", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Egress NACKs : AK : Counts number of Egress packets NACK'ed on to the Horizontal Ring", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xa4", |
| "EventName": "UNC_M2P_TxR_HORZ_NACK.AKC_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", |
| "UMask": "0x80", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Egress NACKs : BL - All", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xa4", |
| "EventName": "UNC_M2P_TxR_HORZ_NACK.BL_ALL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Egress NACKs : BL - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited", |
| "UMask": "0x44", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xa4", |
| "EventName": "UNC_M2P_TxR_HORZ_NACK.BL_CRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Egress NACKs : BL - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", |
| "UMask": "0x40", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xa4", |
| "EventName": "UNC_M2P_TxR_HORZ_NACK.BL_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Egress NACKs : BL - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Egress NACKs : IV", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xa4", |
| "EventName": "UNC_M2P_TxR_HORZ_NACK.IV", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Horizontal Ring", |
| "UMask": "0x8", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xa0", |
| "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AD_ALL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Egress Occupancy : AD - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", |
| "UMask": "0x11", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xa0", |
| "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AD_CRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", |
| "UMask": "0x10", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xa0", |
| "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AD_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Egress Occupancy : AK", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xa0", |
| "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AK", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Egress Occupancy : AK : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xa0", |
| "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AKC_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", |
| "UMask": "0x80", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xa0", |
| "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.BL_ALL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Egress Occupancy : BL - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", |
| "UMask": "0x44", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Credited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xa0", |
| "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.BL_CRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", |
| "UMask": "0x40", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xa0", |
| "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.BL_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Egress Occupancy : IV", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xa0", |
| "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.IV", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Egress Occupancy : IV : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", |
| "UMask": "0x8", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - All", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xa5", |
| "EventName": "UNC_M2P_TxR_HORZ_STARVED.AD_ALL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xa5", |
| "EventName": "UNC_M2P_TxR_HORZ_STARVED.AD_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Egress Injection Starvation : AK", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xa5", |
| "EventName": "UNC_M2P_TxR_HORZ_STARVED.AK", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Egress Injection Starvation : AK : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xa5", |
| "EventName": "UNC_M2P_TxR_HORZ_STARVED.AKC_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", |
| "UMask": "0x80", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - All", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xa5", |
| "EventName": "UNC_M2P_TxR_HORZ_STARVED.BL_ALL", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xa5", |
| "EventName": "UNC_M2P_TxR_HORZ_STARVED.BL_UNCRD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Horizontal Egress Injection Starvation : IV", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xa5", |
| "EventName": "UNC_M2P_TxR_HORZ_STARVED.IV", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Horizontal Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", |
| "UMask": "0x8", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x9c", |
| "EventName": "UNC_M2P_TxR_VERT_ADS_USED.AD_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x9c", |
| "EventName": "UNC_M2P_TxR_VERT_ADS_USED.AD_AG1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", |
| "UMask": "0x10", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x9c", |
| "EventName": "UNC_M2P_TxR_VERT_ADS_USED.BL_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x9c", |
| "EventName": "UNC_M2P_TxR_VERT_ADS_USED.BL_AG1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", |
| "UMask": "0x40", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x9d", |
| "EventName": "UNC_M2P_TxR_VERT_BYPASS.AD_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x9d", |
| "EventName": "UNC_M2P_TxR_VERT_BYPASS.AD_AG1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", |
| "UMask": "0x10", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x9d", |
| "EventName": "UNC_M2P_TxR_VERT_BYPASS.AK_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vertical ADS Used : AK - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x9d", |
| "EventName": "UNC_M2P_TxR_VERT_BYPASS.AK_AG1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vertical ADS Used : AK - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", |
| "UMask": "0x20", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x9d", |
| "EventName": "UNC_M2P_TxR_VERT_BYPASS.BL_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x9d", |
| "EventName": "UNC_M2P_TxR_VERT_BYPASS.BL_AG1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", |
| "UMask": "0x40", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x9d", |
| "EventName": "UNC_M2P_TxR_VERT_BYPASS.IV_AG1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vertical ADS Used : IV - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", |
| "UMask": "0x8", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x9e", |
| "EventName": "UNC_M2P_TxR_VERT_BYPASS_1.AKC_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x9e", |
| "EventName": "UNC_M2P_TxR_VERT_BYPASS_1.AKC_AG1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x94", |
| "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AD_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x94", |
| "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AD_AG1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", |
| "UMask": "0x10", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x94", |
| "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AK_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x94", |
| "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AK_AG1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", |
| "UMask": "0x20", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x94", |
| "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.BL_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x94", |
| "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.BL_AG1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", |
| "UMask": "0x40", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x94", |
| "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.IV_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", |
| "UMask": "0x8", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x95", |
| "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL1.AKC_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x95", |
| "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL1.AKC_AG1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x96", |
| "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AD_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x96", |
| "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AD_AG1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", |
| "UMask": "0x10", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x96", |
| "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AK_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x96", |
| "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AK_AG1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", |
| "UMask": "0x20", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x96", |
| "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.BL_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x96", |
| "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.BL_AG1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", |
| "UMask": "0x40", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x96", |
| "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.IV_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", |
| "UMask": "0x8", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x97", |
| "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE1.AKC_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x97", |
| "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE1.AKC_AG1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x92", |
| "EventName": "UNC_M2P_TxR_VERT_INSERTS0.AD_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x92", |
| "EventName": "UNC_M2P_TxR_VERT_INSERTS0.AD_AG1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", |
| "UMask": "0x10", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x92", |
| "EventName": "UNC_M2P_TxR_VERT_INSERTS0.AK_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x92", |
| "EventName": "UNC_M2P_TxR_VERT_INSERTS0.AK_AG1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", |
| "UMask": "0x20", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x92", |
| "EventName": "UNC_M2P_TxR_VERT_INSERTS0.BL_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x92", |
| "EventName": "UNC_M2P_TxR_VERT_INSERTS0.BL_AG1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", |
| "UMask": "0x40", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x92", |
| "EventName": "UNC_M2P_TxR_VERT_INSERTS0.IV_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vert Egress Allocations : IV - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", |
| "UMask": "0x8", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x93", |
| "EventName": "UNC_M2P_TxR_VERT_INSERTS1.AKC_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x93", |
| "EventName": "UNC_M2P_TxR_VERT_INSERTS1.AKC_AG1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x98", |
| "EventName": "UNC_M2P_TxR_VERT_NACK0.AD_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x98", |
| "EventName": "UNC_M2P_TxR_VERT_NACK0.AD_AG1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring", |
| "UMask": "0x10", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x98", |
| "EventName": "UNC_M2P_TxR_VERT_NACK0.AK_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x98", |
| "EventName": "UNC_M2P_TxR_VERT_NACK0.AK_AG1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring", |
| "UMask": "0x20", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x98", |
| "EventName": "UNC_M2P_TxR_VERT_NACK0.BL_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x98", |
| "EventName": "UNC_M2P_TxR_VERT_NACK0.BL_AG1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring", |
| "UMask": "0x40", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Vertical Egress NACKs : IV", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x98", |
| "EventName": "UNC_M2P_TxR_VERT_NACK0.IV_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vertical Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Vertical Ring", |
| "UMask": "0x8", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x99", |
| "EventName": "UNC_M2P_TxR_VERT_NACK1.AKC_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x99", |
| "EventName": "UNC_M2P_TxR_VERT_NACK1.AKC_AG1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x90", |
| "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AD_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x90", |
| "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AD_AG1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", |
| "UMask": "0x10", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x90", |
| "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AK_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x90", |
| "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AK_AG1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", |
| "UMask": "0x20", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x90", |
| "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.BL_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x90", |
| "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.BL_AG1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", |
| "UMask": "0x40", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x90", |
| "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.IV_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vert Egress Occupancy : IV - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", |
| "UMask": "0x8", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x91", |
| "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY1.AKC_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x91", |
| "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY1.AKC_AG1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x9a", |
| "EventName": "UNC_M2P_TxR_VERT_STARVED0.AD_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x9a", |
| "EventName": "UNC_M2P_TxR_VERT_STARVED0.AD_AG1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", |
| "UMask": "0x10", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x9a", |
| "EventName": "UNC_M2P_TxR_VERT_STARVED0.AK_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x9a", |
| "EventName": "UNC_M2P_TxR_VERT_STARVED0.AK_AG1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", |
| "UMask": "0x20", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x9a", |
| "EventName": "UNC_M2P_TxR_VERT_STARVED0.BL_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x9a", |
| "EventName": "UNC_M2P_TxR_VERT_STARVED0.BL_AG1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", |
| "UMask": "0x40", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Vertical Egress Injection Starvation : IV", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x9a", |
| "EventName": "UNC_M2P_TxR_VERT_STARVED0.IV_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vertical Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", |
| "UMask": "0x8", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x9b", |
| "EventName": "UNC_M2P_TxR_VERT_STARVED1.AKC_AG0", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x9b", |
| "EventName": "UNC_M2P_TxR_VERT_STARVED1.AKC_AG1", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x9b", |
| "EventName": "UNC_M2P_TxR_VERT_STARVED1.TGC", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Vertical AD Ring In Use : Down and Even", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xb0", |
| "EventName": "UNC_M2P_VERT_RING_AD_IN_USE.DN_EVEN", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Vertical AD Ring In Use : Down and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Vertical AD Ring In Use : Down and Odd", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xb0", |
| "EventName": "UNC_M2P_VERT_RING_AD_IN_USE.DN_ODD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Vertical AD Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x8", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Vertical AD Ring In Use : Up and Even", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xb0", |
| "EventName": "UNC_M2P_VERT_RING_AD_IN_USE.UP_EVEN", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Vertical AD Ring In Use : Up and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Vertical AD Ring In Use : Up and Odd", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xb0", |
| "EventName": "UNC_M2P_VERT_RING_AD_IN_USE.UP_ODD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Vertical AD Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Vertical AKC Ring In Use : Down and Even", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xb4", |
| "EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.DN_EVEN", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Vertical AKC Ring In Use : Down and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Vertical AKC Ring In Use : Down and Odd", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xb4", |
| "EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.DN_ODD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Vertical AKC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x8", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Vertical AKC Ring In Use : Up and Even", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xb4", |
| "EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.UP_EVEN", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Vertical AKC Ring In Use : Up and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Vertical AKC Ring In Use : Up and Odd", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xb4", |
| "EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.UP_ODD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Vertical AKC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Vertical AK Ring In Use : Down and Even", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xb1", |
| "EventName": "UNC_M2P_VERT_RING_AK_IN_USE.DN_EVEN", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Vertical AK Ring In Use : Down and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Vertical AK Ring In Use : Down and Odd", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xb1", |
| "EventName": "UNC_M2P_VERT_RING_AK_IN_USE.DN_ODD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Vertical AK Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x8", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Vertical AK Ring In Use : Up and Even", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xb1", |
| "EventName": "UNC_M2P_VERT_RING_AK_IN_USE.UP_EVEN", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Vertical AK Ring In Use : Up and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Vertical AK Ring In Use : Up and Odd", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xb1", |
| "EventName": "UNC_M2P_VERT_RING_AK_IN_USE.UP_ODD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Vertical AK Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Vertical BL Ring in Use : Down and Even", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xb2", |
| "EventName": "UNC_M2P_VERT_RING_BL_IN_USE.DN_EVEN", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Vertical BL Ring in Use : Down and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Vertical BL Ring in Use : Down and Odd", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xb2", |
| "EventName": "UNC_M2P_VERT_RING_BL_IN_USE.DN_ODD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Vertical BL Ring in Use : Down and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x8", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Vertical BL Ring in Use : Up and Even", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xb2", |
| "EventName": "UNC_M2P_VERT_RING_BL_IN_USE.UP_EVEN", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Vertical BL Ring in Use : Up and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Vertical BL Ring in Use : Up and Odd", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xb2", |
| "EventName": "UNC_M2P_VERT_RING_BL_IN_USE.UP_ODD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Vertical BL Ring in Use : Up and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Vertical IV Ring in Use : Down", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xb3", |
| "EventName": "UNC_M2P_VERT_RING_IV_IN_USE.DN", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Vertical IV Ring in Use : Down : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Vertical IV Ring in Use : Up", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xb3", |
| "EventName": "UNC_M2P_VERT_RING_IV_IN_USE.UP", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Vertical IV Ring in Use : Up : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Vertical TGC Ring In Use : Down and Even", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xb5", |
| "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.DN_EVEN", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Vertical TGC Ring In Use : Down and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x4", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Vertical TGC Ring In Use : Down and Odd", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xb5", |
| "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.DN_ODD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Vertical TGC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x8", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Vertical TGC Ring In Use : Up and Even", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xb5", |
| "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.UP_EVEN", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Vertical TGC Ring In Use : Up and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x1", |
| "Unit": "M2PCIe" |
| }, |
| { |
| "BriefDescription": "Vertical TGC Ring In Use : Up and Odd", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xb5", |
| "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.UP_ODD", |
| "Experimental": "1", |
| "PerPkg": "1", |
| "PublicDescription": "Vertical TGC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", |
| "UMask": "0x2", |
| "Unit": "M2PCIe" |
| } |
| ] |
