| /* |
| * P2020 RDB Core0 Device Tree Source in CAMP mode. |
| * |
| * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache |
| * can be shared, all the other devices must be assigned to one core only. |
| * This dts file allows core0 to have memory, l2, i2c, spi, gpio, dma1, usb, |
| * eth1, eth2, sdhc, crypto, global-util, pci0. |
| * |
| * Copyright 2009 Freescale Semiconductor Inc. |
| * |
| * This program is free software; you can redistribute it and/or modify it |
| * under the terms of the GNU General Public License as published by the |
| * Free Software Foundation; either version 2 of the License, or (at your |
| * option) any later version. |
| */ |
| |
| /dts-v1/; |
| / { |
| model = "fsl,P2020"; |
| compatible = "fsl,P2020RDB", "fsl,MPC85XXRDB-CAMP"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| aliases { |
| ethernet1 = &enet1; |
| ethernet2 = &enet2; |
| serial0 = &serial0; |
| pci0 = &pci0; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| PowerPC,P2020@0 { |
| device_type = "cpu"; |
| reg = <0x0>; |
| next-level-cache = <&L2>; |
| }; |
| }; |
| |
| memory { |
| device_type = "memory"; |
| }; |
| |
| soc@ffe00000 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| device_type = "soc"; |
| compatible = "fsl,p2020-immr", "simple-bus"; |
| ranges = <0x0 0x0 0xffe00000 0x100000>; |
| bus-frequency = <0>; // Filled out by uboot. |
| |
| ecm-law@0 { |
| compatible = "fsl,ecm-law"; |
| reg = <0x0 0x1000>; |
| fsl,num-laws = <12>; |
| }; |
| |
| ecm@1000 { |
| compatible = "fsl,p2020-ecm", "fsl,ecm"; |
| reg = <0x1000 0x1000>; |
| interrupts = <17 2>; |
| interrupt-parent = <&mpic>; |
| }; |
| |
| memory-controller@2000 { |
| compatible = "fsl,p2020-memory-controller"; |
| reg = <0x2000 0x1000>; |
| interrupt-parent = <&mpic>; |
| interrupts = <18 2>; |
| }; |
| |
| i2c@3000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| cell-index = <0>; |
| compatible = "fsl-i2c"; |
| reg = <0x3000 0x100>; |
| interrupts = <43 2>; |
| interrupt-parent = <&mpic>; |
| dfsrr; |
| rtc@68 { |
| compatible = "dallas,ds1339"; |
| reg = <0x68>; |
| }; |
| }; |
| |
| i2c@3100 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| cell-index = <1>; |
| compatible = "fsl-i2c"; |
| reg = <0x3100 0x100>; |
| interrupts = <43 2>; |
| interrupt-parent = <&mpic>; |
| dfsrr; |
| }; |
| |
| serial0: serial@4500 { |
| cell-index = <0>; |
| device_type = "serial"; |
| compatible = "ns16550"; |
| reg = <0x4500 0x100>; |
| clock-frequency = <0>; |
| }; |
| |
| spi@7000 { |
| cell-index = <0>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "fsl,espi"; |
| reg = <0x7000 0x1000>; |
| interrupts = <59 0x2>; |
| interrupt-parent = <&mpic>; |
| mode = "cpu"; |
| |
| fsl_m25p80@0 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "fsl,espi-flash"; |
| reg = <0>; |
| linux,modalias = "fsl_m25p80"; |
| modal = "s25sl128b"; |
| spi-max-frequency = <50000000>; |
| mode = <0>; |
| |
| partition@0 { |
| /* 512KB for u-boot Bootloader Image */ |
| reg = <0x0 0x00080000>; |
| label = "SPI (RO) U-Boot Image"; |
| read-only; |
| }; |
| |
| partition@80000 { |
| /* 512KB for DTB Image */ |
| reg = <0x00080000 0x00080000>; |
| label = "SPI (RO) DTB Image"; |
| read-only; |
| }; |
| |
| partition@100000 { |
| /* 4MB for Linux Kernel Image */ |
| reg = <0x00100000 0x00400000>; |
| label = "SPI (RO) Linux Kernel Image"; |
| read-only; |
| }; |
| |
| partition@500000 { |
| /* 4MB for Compressed RFS Image */ |
| reg = <0x00500000 0x00400000>; |
| label = "SPI (RO) Compressed RFS Image"; |
| read-only; |
| }; |
| |
| partition@900000 { |
| /* 7MB for JFFS2 based RFS */ |
| reg = <0x00900000 0x00700000>; |
| label = "SPI (RW) JFFS2 RFS"; |
| }; |
| }; |
| }; |
| |
| gpio: gpio-controller@f000 { |
| #gpio-cells = <2>; |
| compatible = "fsl,mpc8572-gpio"; |
| reg = <0xf000 0x100>; |
| interrupts = <47 0x2>; |
| interrupt-parent = <&mpic>; |
| gpio-controller; |
| }; |
| |
| L2: l2-cache-controller@20000 { |
| compatible = "fsl,p2020-l2-cache-controller"; |
| reg = <0x20000 0x1000>; |
| cache-line-size = <32>; // 32 bytes |
| cache-size = <0x80000>; // L2,512K |
| interrupt-parent = <&mpic>; |
| interrupts = <16 2>; |
| }; |
| |
| dma@21300 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "fsl,eloplus-dma"; |
| reg = <0x21300 0x4>; |
| ranges = <0x0 0x21100 0x200>; |
| cell-index = <0>; |
| dma-channel@0 { |
| compatible = "fsl,eloplus-dma-channel"; |
| reg = <0x0 0x80>; |
| cell-index = <0>; |
| interrupt-parent = <&mpic>; |
| interrupts = <20 2>; |
| }; |
| dma-channel@80 { |
| compatible = "fsl,eloplus-dma-channel"; |
| reg = <0x80 0x80>; |
| cell-index = <1>; |
| interrupt-parent = <&mpic>; |
| interrupts = <21 2>; |
| }; |
| dma-channel@100 { |
| compatible = "fsl,eloplus-dma-channel"; |
| reg = <0x100 0x80>; |
| cell-index = <2>; |
| interrupt-parent = <&mpic>; |
| interrupts = <22 2>; |
| }; |
| dma-channel@180 { |
| compatible = "fsl,eloplus-dma-channel"; |
| reg = <0x180 0x80>; |
| cell-index = <3>; |
| interrupt-parent = <&mpic>; |
| interrupts = <23 2>; |
| }; |
| }; |
| |
| usb@22000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "fsl-usb2-dr"; |
| reg = <0x22000 0x1000>; |
| interrupt-parent = <&mpic>; |
| interrupts = <28 0x2>; |
| phy_type = "ulpi"; |
| }; |
| |
| mdio@24520 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "fsl,gianfar-mdio"; |
| reg = <0x24520 0x20>; |
| |
| phy0: ethernet-phy@0 { |
| interrupt-parent = <&mpic>; |
| interrupts = <3 1>; |
| reg = <0x0>; |
| }; |
| phy1: ethernet-phy@1 { |
| interrupt-parent = <&mpic>; |
| interrupts = <3 1>; |
| reg = <0x1>; |
| }; |
| }; |
| |
| mdio@25520 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "fsl,gianfar-tbi"; |
| reg = <0x26520 0x20>; |
| |
| tbi0: tbi-phy@11 { |
| reg = <0x11>; |
| device_type = "tbi-phy"; |
| }; |
| }; |
| |
| enet1: ethernet@25000 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| cell-index = <1>; |
| device_type = "network"; |
| model = "eTSEC"; |
| compatible = "gianfar"; |
| reg = <0x25000 0x1000>; |
| ranges = <0x0 0x25000 0x1000>; |
| local-mac-address = [ 00 00 00 00 00 00 ]; |
| interrupts = <35 2 36 2 40 2>; |
| interrupt-parent = <&mpic>; |
| tbi-handle = <&tbi0>; |
| phy-handle = <&phy0>; |
| phy-connection-type = "sgmii"; |
| |
| }; |
| |
| enet2: ethernet@26000 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| cell-index = <2>; |
| device_type = "network"; |
| model = "eTSEC"; |
| compatible = "gianfar"; |
| reg = <0x26000 0x1000>; |
| ranges = <0x0 0x26000 0x1000>; |
| local-mac-address = [ 00 00 00 00 00 00 ]; |
| interrupts = <31 2 32 2 33 2>; |
| interrupt-parent = <&mpic>; |
| phy-handle = <&phy1>; |
| phy-connection-type = "rgmii-id"; |
| }; |
| |
| sdhci@2e000 { |
| compatible = "fsl,p2020-esdhc", "fsl,esdhc"; |
| reg = <0x2e000 0x1000>; |
| interrupts = <72 0x2>; |
| interrupt-parent = <&mpic>; |
| /* Filled in by U-Boot */ |
| clock-frequency = <0>; |
| }; |
| |
| crypto@30000 { |
| compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4", |
| "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0"; |
| reg = <0x30000 0x10000>; |
| interrupts = <45 2 58 2>; |
| interrupt-parent = <&mpic>; |
| fsl,num-channels = <4>; |
| fsl,channel-fifo-len = <24>; |
| fsl,exec-units-mask = <0xbfe>; |
| fsl,descriptor-types-mask = <0x3ab0ebf>; |
| }; |
| |
| mpic: pic@40000 { |
| interrupt-controller; |
| #address-cells = <0>; |
| #interrupt-cells = <2>; |
| reg = <0x40000 0x40000>; |
| compatible = "chrp,open-pic"; |
| device_type = "open-pic"; |
| protected-sources = < |
| 42 76 77 78 79 /* serial1 , dma2 */ |
| 29 30 34 26 /* enet0, pci1 */ |
| 0xe0 0xe1 0xe2 0xe3 /* msi */ |
| 0xe4 0xe5 0xe6 0xe7 |
| >; |
| }; |
| |
| global-utilities@e0000 { |
| compatible = "fsl,p2020-guts"; |
| reg = <0xe0000 0x1000>; |
| fsl,has-rstcr; |
| }; |
| }; |
| |
| pci0: pcie@ffe09000 { |
| compatible = "fsl,mpc8548-pcie"; |
| device_type = "pci"; |
| #interrupt-cells = <1>; |
| #size-cells = <2>; |
| #address-cells = <3>; |
| reg = <0 0xffe09000 0 0x1000>; |
| bus-range = <0 255>; |
| ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 |
| 0x1000000 0x0 0x00000000 0 0xffc30000 0x0 0x10000>; |
| clock-frequency = <33333333>; |
| interrupt-parent = <&mpic>; |
| interrupts = <25 2>; |
| pcie@0 { |
| reg = <0x0 0x0 0x0 0x0 0x0>; |
| #size-cells = <2>; |
| #address-cells = <3>; |
| device_type = "pci"; |
| ranges = <0x2000000 0x0 0xa0000000 |
| 0x2000000 0x0 0xa0000000 |
| 0x0 0x20000000 |
| |
| 0x1000000 0x0 0x0 |
| 0x1000000 0x0 0x0 |
| 0x0 0x100000>; |
| }; |
| }; |
| }; |
