| /* |
| * Copyright (C) 2021 Advanced Micro Devices, Inc. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice shall be included |
| * in all copies or substantial portions of the Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN |
| * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
| * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| */ |
| #ifndef _mp_11_0_8_SH_MASK_HEADER |
| #define _mp_11_0_8_SH_MASK_HEADER |
| |
| #define MP0_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_100__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_101__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_102__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_103__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_32__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_33__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_34__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_35__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_36__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_37__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_38__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_39__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_40__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_41__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_42__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_43__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_44__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_45__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_46__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_47__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_48__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_49__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_50__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_51__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_52__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_53__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_54__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_55__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_56__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_57__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_58__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_59__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_60__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_61__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_62__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_63__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_64__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_65__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_66__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_67__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_68__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_69__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_70__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_71__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_72__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_73__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_74__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_75__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_76__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_77__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_78__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_79__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_80__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_81__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_82__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_83__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_84__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_85__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_86__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_87__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_88__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_89__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_90__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_91__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_92__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_93__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_94__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_95__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_96__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_97__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_98__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL |
| #define MP0_SMN_C2PMSG_99__CONTENT__SHIFT 0x0 |
| #define MP0_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L |
| #define MP0_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10 |
| #define MP0_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L |
| #define MP0_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 |
| #define MP0_SMN_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L |
| #define MP0_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8 |
| #define MP0_SMN_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L |
| #define MP0_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0 |
| #define MP0_SMN_IH_SW_INT__ID_MASK 0x000000FFL |
| #define MP0_SMN_IH_SW_INT__ID__SHIFT 0x0 |
| #define MP0_SMN_IH_SW_INT__VALID_MASK 0x00000100L |
| #define MP0_SMN_IH_SW_INT__VALID__SHIFT 0x8 |
| #define MP1_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_100__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_101__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_102__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_103__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_32__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_33__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_34__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_35__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_36__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_37__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_38__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_39__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_40__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_41__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_42__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_43__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_44__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_45__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_46__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_47__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_48__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_49__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_50__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_51__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_52__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_53__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_54__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_55__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_56__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_57__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_58__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_59__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_60__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_61__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_62__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_63__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_64__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_65__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_66__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_67__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_68__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_69__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_70__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_71__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_72__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_73__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_74__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_75__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_76__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_77__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_78__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_79__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_80__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_81__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_82__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_83__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_84__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_85__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_86__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_87__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_88__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_89__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_90__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_91__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_92__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_93__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_94__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_95__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_96__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_97__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_98__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_C2PMSG_99__CONTENT__SHIFT 0x0 |
| #define MP1_SMN_EXT_SCRATCH0__DATA_MASK 0xFFFFFFFFL |
| #define MP1_SMN_EXT_SCRATCH0__DATA__SHIFT 0x0 |
| #define MP1_SMN_EXT_SCRATCH1__DATA_MASK 0xFFFFFFFFL |
| #define MP1_SMN_EXT_SCRATCH1__DATA__SHIFT 0x0 |
| #define MP1_SMN_EXT_SCRATCH2__DATA_MASK 0xFFFFFFFFL |
| #define MP1_SMN_EXT_SCRATCH2__DATA__SHIFT 0x0 |
| #define MP1_SMN_EXT_SCRATCH3__DATA_MASK 0xFFFFFFFFL |
| #define MP1_SMN_EXT_SCRATCH3__DATA__SHIFT 0x0 |
| #define MP1_SMN_EXT_SCRATCH4__DATA_MASK 0xFFFFFFFFL |
| #define MP1_SMN_EXT_SCRATCH4__DATA__SHIFT 0x0 |
| #define MP1_SMN_EXT_SCRATCH5__DATA_MASK 0xFFFFFFFFL |
| #define MP1_SMN_EXT_SCRATCH5__DATA__SHIFT 0x0 |
| #define MP1_SMN_EXT_SCRATCH6__DATA_MASK 0xFFFFFFFFL |
| #define MP1_SMN_EXT_SCRATCH6__DATA__SHIFT 0x0 |
| #define MP1_SMN_EXT_SCRATCH7__DATA_MASK 0xFFFFFFFFL |
| #define MP1_SMN_EXT_SCRATCH7__DATA__SHIFT 0x0 |
| #define MP1_SMN_FPS_CNT__COUNT_MASK 0xFFFFFFFFL |
| #define MP1_SMN_FPS_CNT__COUNT__SHIFT 0x0 |
| #define MP1_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L |
| #define MP1_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10 |
| #define MP1_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L |
| #define MP1_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 |
| #define MP1_SMN_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L |
| #define MP1_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8 |
| #define MP1_SMN_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L |
| #define MP1_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0 |
| #define MP1_SMN_IH_SW_INT__ID_MASK 0x000000FFL |
| #define MP1_SMN_IH_SW_INT__ID__SHIFT 0x0 |
| #define MP1_SMN_IH_SW_INT__VALID_MASK 0x00000100L |
| #define MP1_SMN_IH_SW_INT__VALID__SHIFT 0x8 |
| |
| #endif |
