| // SPDX-License-Identifier: (GPL-2.0 OR MIT) |
| /* |
| * Copyright (C) 2020 MediaTek Inc. |
| * Author: Seiya Wang <seiya.wang@mediatek.com> |
| */ |
| |
| /dts-v1/; |
| #include <dt-bindings/clock/mt8192-clk.h> |
| #include <dt-bindings/gce/mt8192-gce.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/interrupt-controller/irq.h> |
| #include <dt-bindings/memory/mt8192-larb-port.h> |
| #include <dt-bindings/pinctrl/mt8192-pinfunc.h> |
| #include <dt-bindings/phy/phy.h> |
| #include <dt-bindings/power/mt8192-power.h> |
| #include <dt-bindings/reset/mt8192-resets.h> |
| |
| / { |
| compatible = "mediatek,mt8192"; |
| interrupt-parent = <&gic>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| aliases { |
| ovl0 = &ovl0; |
| ovl-2l0 = &ovl_2l0; |
| ovl-2l2 = &ovl_2l2; |
| rdma0 = &rdma0; |
| rdma4 = &rdma4; |
| }; |
| |
| clk26m: oscillator0 { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <26000000>; |
| clock-output-names = "clk26m"; |
| }; |
| |
| clk32k: oscillator1 { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <32768>; |
| clock-output-names = "clk32k"; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a55"; |
| reg = <0x000>; |
| enable-method = "psci"; |
| clock-frequency = <1701000000>; |
| cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>; |
| next-level-cache = <&l2_0>; |
| capacity-dmips-mhz = <530>; |
| }; |
| |
| cpu1: cpu@100 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a55"; |
| reg = <0x100>; |
| enable-method = "psci"; |
| clock-frequency = <1701000000>; |
| cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>; |
| next-level-cache = <&l2_0>; |
| capacity-dmips-mhz = <530>; |
| }; |
| |
| cpu2: cpu@200 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a55"; |
| reg = <0x200>; |
| enable-method = "psci"; |
| clock-frequency = <1701000000>; |
| cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>; |
| next-level-cache = <&l2_0>; |
| capacity-dmips-mhz = <530>; |
| }; |
| |
| cpu3: cpu@300 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a55"; |
| reg = <0x300>; |
| enable-method = "psci"; |
| clock-frequency = <1701000000>; |
| cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>; |
| next-level-cache = <&l2_0>; |
| capacity-dmips-mhz = <530>; |
| }; |
| |
| cpu4: cpu@400 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a76"; |
| reg = <0x400>; |
| enable-method = "psci"; |
| clock-frequency = <2171000000>; |
| cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>; |
| next-level-cache = <&l2_1>; |
| capacity-dmips-mhz = <1024>; |
| }; |
| |
| cpu5: cpu@500 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a76"; |
| reg = <0x500>; |
| enable-method = "psci"; |
| clock-frequency = <2171000000>; |
| cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>; |
| next-level-cache = <&l2_1>; |
| capacity-dmips-mhz = <1024>; |
| }; |
| |
| cpu6: cpu@600 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a76"; |
| reg = <0x600>; |
| enable-method = "psci"; |
| clock-frequency = <2171000000>; |
| cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>; |
| next-level-cache = <&l2_1>; |
| capacity-dmips-mhz = <1024>; |
| }; |
| |
| cpu7: cpu@700 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a76"; |
| reg = <0x700>; |
| enable-method = "psci"; |
| clock-frequency = <2171000000>; |
| cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>; |
| next-level-cache = <&l2_1>; |
| capacity-dmips-mhz = <1024>; |
| }; |
| |
| cpu-map { |
| cluster0 { |
| core0 { |
| cpu = <&cpu0>; |
| }; |
| core1 { |
| cpu = <&cpu1>; |
| }; |
| core2 { |
| cpu = <&cpu2>; |
| }; |
| core3 { |
| cpu = <&cpu3>; |
| }; |
| }; |
| |
| cluster1 { |
| core0 { |
| cpu = <&cpu4>; |
| }; |
| core1 { |
| cpu = <&cpu5>; |
| }; |
| core2 { |
| cpu = <&cpu6>; |
| }; |
| core3 { |
| cpu = <&cpu7>; |
| }; |
| }; |
| }; |
| |
| l2_0: l2-cache0 { |
| compatible = "cache"; |
| cache-level = <2>; |
| next-level-cache = <&l3_0>; |
| }; |
| |
| l2_1: l2-cache1 { |
| compatible = "cache"; |
| cache-level = <2>; |
| next-level-cache = <&l3_0>; |
| }; |
| |
| l3_0: l3-cache { |
| compatible = "cache"; |
| cache-level = <3>; |
| }; |
| |
| idle-states { |
| entry-method = "psci"; |
| cpu_sleep_l: cpu-sleep-l { |
| compatible = "arm,idle-state"; |
| arm,psci-suspend-param = <0x00010001>; |
| local-timer-stop; |
| entry-latency-us = <55>; |
| exit-latency-us = <140>; |
| min-residency-us = <780>; |
| }; |
| cpu_sleep_b: cpu-sleep-b { |
| compatible = "arm,idle-state"; |
| arm,psci-suspend-param = <0x00010001>; |
| local-timer-stop; |
| entry-latency-us = <35>; |
| exit-latency-us = <145>; |
| min-residency-us = <720>; |
| }; |
| cluster_sleep_l: cluster-sleep-l { |
| compatible = "arm,idle-state"; |
| arm,psci-suspend-param = <0x01010002>; |
| local-timer-stop; |
| entry-latency-us = <60>; |
| exit-latency-us = <155>; |
| min-residency-us = <860>; |
| }; |
| cluster_sleep_b: cluster-sleep-b { |
| compatible = "arm,idle-state"; |
| arm,psci-suspend-param = <0x01010002>; |
| local-timer-stop; |
| entry-latency-us = <40>; |
| exit-latency-us = <155>; |
| min-residency-us = <780>; |
| }; |
| }; |
| }; |
| |
| pmu-a55 { |
| compatible = "arm,cortex-a55-pmu"; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; |
| }; |
| |
| pmu-a76 { |
| compatible = "arm,cortex-a76-pmu"; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; |
| }; |
| |
| psci { |
| compatible = "arm,psci-1.0"; |
| method = "smc"; |
| }; |
| |
| timer: timer { |
| compatible = "arm,armv8-timer"; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, |
| <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, |
| <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, |
| <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>; |
| clock-frequency = <13000000>; |
| }; |
| |
| soc { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| compatible = "simple-bus"; |
| ranges; |
| |
| gic: interrupt-controller@c000000 { |
| compatible = "arm,gic-v3"; |
| #interrupt-cells = <4>; |
| #redistributor-regions = <1>; |
| interrupt-parent = <&gic>; |
| interrupt-controller; |
| reg = <0 0x0c000000 0 0x40000>, |
| <0 0x0c040000 0 0x200000>; |
| interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; |
| |
| ppi-partitions { |
| ppi_cluster0: interrupt-partition-0 { |
| affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; |
| }; |
| ppi_cluster1: interrupt-partition-1 { |
| affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; |
| }; |
| }; |
| }; |
| |
| topckgen: syscon@10000000 { |
| compatible = "mediatek,mt8192-topckgen", "syscon"; |
| reg = <0 0x10000000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| infracfg: syscon@10001000 { |
| compatible = "mediatek,mt8192-infracfg", "syscon"; |
| reg = <0 0x10001000 0 0x1000>; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| }; |
| |
| pericfg: syscon@10003000 { |
| compatible = "mediatek,mt8192-pericfg", "syscon"; |
| reg = <0 0x10003000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| pio: pinctrl@10005000 { |
| compatible = "mediatek,mt8192-pinctrl"; |
| reg = <0 0x10005000 0 0x1000>, |
| <0 0x11c20000 0 0x1000>, |
| <0 0x11d10000 0 0x1000>, |
| <0 0x11d30000 0 0x1000>, |
| <0 0x11d40000 0 0x1000>, |
| <0 0x11e20000 0 0x1000>, |
| <0 0x11e70000 0 0x1000>, |
| <0 0x11ea0000 0 0x1000>, |
| <0 0x11f20000 0 0x1000>, |
| <0 0x11f30000 0 0x1000>, |
| <0 0x1000b000 0 0x1000>; |
| reg-names = "iocfg0", "iocfg_rm", "iocfg_bm", |
| "iocfg_bl", "iocfg_br", "iocfg_lm", |
| "iocfg_lb", "iocfg_rt", "iocfg_lt", |
| "iocfg_tl", "eint"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = <&pio 0 0 220>; |
| interrupt-controller; |
| interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>; |
| #interrupt-cells = <2>; |
| }; |
| |
| scpsys: syscon@10006000 { |
| compatible = "mediatek,mt8192-scpsys", "syscon", "simple-mfd"; |
| reg = <0 0x10006000 0 0x1000>; |
| |
| /* System Power Manager */ |
| spm: power-controller { |
| compatible = "mediatek,mt8192-power-controller"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| #power-domain-cells = <1>; |
| |
| /* power domain of the SoC */ |
| power-domain@MT8192_POWER_DOMAIN_AUDIO { |
| reg = <MT8192_POWER_DOMAIN_AUDIO>; |
| clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>, |
| <&infracfg CLK_INFRA_AUDIO_26M_B>, |
| <&infracfg CLK_INFRA_AUDIO>; |
| clock-names = "audio", "audio1", "audio2"; |
| mediatek,infracfg = <&infracfg>; |
| #power-domain-cells = <0>; |
| }; |
| |
| power-domain@MT8192_POWER_DOMAIN_CONN { |
| reg = <MT8192_POWER_DOMAIN_CONN>; |
| clocks = <&infracfg CLK_INFRA_PMIC_CONN>; |
| clock-names = "conn"; |
| mediatek,infracfg = <&infracfg>; |
| #power-domain-cells = <0>; |
| }; |
| |
| power-domain@MT8192_POWER_DOMAIN_MFG0 { |
| reg = <MT8192_POWER_DOMAIN_MFG0>; |
| clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>; |
| clock-names = "mfg"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| #power-domain-cells = <1>; |
| |
| power-domain@MT8192_POWER_DOMAIN_MFG1 { |
| reg = <MT8192_POWER_DOMAIN_MFG1>; |
| mediatek,infracfg = <&infracfg>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| #power-domain-cells = <1>; |
| |
| power-domain@MT8192_POWER_DOMAIN_MFG2 { |
| reg = <MT8192_POWER_DOMAIN_MFG2>; |
| #power-domain-cells = <0>; |
| }; |
| |
| power-domain@MT8192_POWER_DOMAIN_MFG3 { |
| reg = <MT8192_POWER_DOMAIN_MFG3>; |
| #power-domain-cells = <0>; |
| }; |
| |
| power-domain@MT8192_POWER_DOMAIN_MFG4 { |
| reg = <MT8192_POWER_DOMAIN_MFG4>; |
| #power-domain-cells = <0>; |
| }; |
| |
| power-domain@MT8192_POWER_DOMAIN_MFG5 { |
| reg = <MT8192_POWER_DOMAIN_MFG5>; |
| #power-domain-cells = <0>; |
| }; |
| |
| power-domain@MT8192_POWER_DOMAIN_MFG6 { |
| reg = <MT8192_POWER_DOMAIN_MFG6>; |
| #power-domain-cells = <0>; |
| }; |
| }; |
| }; |
| |
| power-domain@MT8192_POWER_DOMAIN_DISP { |
| reg = <MT8192_POWER_DOMAIN_DISP>; |
| clocks = <&topckgen CLK_TOP_DISP_SEL>, |
| <&mmsys CLK_MM_SMI_INFRA>, |
| <&mmsys CLK_MM_SMI_COMMON>, |
| <&mmsys CLK_MM_SMI_GALS>, |
| <&mmsys CLK_MM_SMI_IOMMU>; |
| clock-names = "disp", "disp-0", "disp-1", "disp-2", |
| "disp-3"; |
| mediatek,infracfg = <&infracfg>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| #power-domain-cells = <1>; |
| |
| power-domain@MT8192_POWER_DOMAIN_IPE { |
| reg = <MT8192_POWER_DOMAIN_IPE>; |
| clocks = <&topckgen CLK_TOP_IPE_SEL>, |
| <&ipesys CLK_IPE_LARB19>, |
| <&ipesys CLK_IPE_LARB20>, |
| <&ipesys CLK_IPE_SMI_SUBCOM>, |
| <&ipesys CLK_IPE_GALS>; |
| clock-names = "ipe", "ipe-0", "ipe-1", "ipe-2", |
| "ipe-3"; |
| mediatek,infracfg = <&infracfg>; |
| #power-domain-cells = <0>; |
| }; |
| |
| power-domain@MT8192_POWER_DOMAIN_ISP { |
| reg = <MT8192_POWER_DOMAIN_ISP>; |
| clocks = <&topckgen CLK_TOP_IMG1_SEL>, |
| <&imgsys CLK_IMG_LARB9>, |
| <&imgsys CLK_IMG_GALS>; |
| clock-names = "isp", "isp-0", "isp-1"; |
| mediatek,infracfg = <&infracfg>; |
| #power-domain-cells = <0>; |
| }; |
| |
| power-domain@MT8192_POWER_DOMAIN_ISP2 { |
| reg = <MT8192_POWER_DOMAIN_ISP2>; |
| clocks = <&topckgen CLK_TOP_IMG2_SEL>, |
| <&imgsys2 CLK_IMG2_LARB11>, |
| <&imgsys2 CLK_IMG2_GALS>; |
| clock-names = "isp2", "isp2-0", "isp2-1"; |
| mediatek,infracfg = <&infracfg>; |
| #power-domain-cells = <0>; |
| }; |
| |
| power-domain@MT8192_POWER_DOMAIN_MDP { |
| reg = <MT8192_POWER_DOMAIN_MDP>; |
| clocks = <&topckgen CLK_TOP_MDP_SEL>, |
| <&mdpsys CLK_MDP_SMI0>; |
| clock-names = "mdp", "mdp-0"; |
| mediatek,infracfg = <&infracfg>; |
| #power-domain-cells = <0>; |
| }; |
| |
| power-domain@MT8192_POWER_DOMAIN_VENC { |
| reg = <MT8192_POWER_DOMAIN_VENC>; |
| clocks = <&topckgen CLK_TOP_VENC_SEL>, |
| <&vencsys CLK_VENC_SET1_VENC>; |
| clock-names = "venc", "venc-0"; |
| mediatek,infracfg = <&infracfg>; |
| #power-domain-cells = <0>; |
| }; |
| |
| power-domain@MT8192_POWER_DOMAIN_VDEC { |
| reg = <MT8192_POWER_DOMAIN_VDEC>; |
| clocks = <&topckgen CLK_TOP_VDEC_SEL>, |
| <&vdecsys_soc CLK_VDEC_SOC_VDEC>, |
| <&vdecsys_soc CLK_VDEC_SOC_LAT>, |
| <&vdecsys_soc CLK_VDEC_SOC_LARB1>; |
| clock-names = "vdec", "vdec-0", "vdec-1", "vdec-2"; |
| mediatek,infracfg = <&infracfg>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| #power-domain-cells = <1>; |
| |
| power-domain@MT8192_POWER_DOMAIN_VDEC2 { |
| reg = <MT8192_POWER_DOMAIN_VDEC2>; |
| clocks = <&vdecsys CLK_VDEC_VDEC>, |
| <&vdecsys CLK_VDEC_LAT>, |
| <&vdecsys CLK_VDEC_LARB1>; |
| clock-names = "vdec2-0", "vdec2-1", |
| "vdec2-2"; |
| #power-domain-cells = <0>; |
| }; |
| }; |
| |
| power-domain@MT8192_POWER_DOMAIN_CAM { |
| reg = <MT8192_POWER_DOMAIN_CAM>; |
| clocks = <&topckgen CLK_TOP_CAM_SEL>, |
| <&camsys CLK_CAM_LARB13>, |
| <&camsys CLK_CAM_LARB14>, |
| <&camsys CLK_CAM_CCU_GALS>, |
| <&camsys CLK_CAM_CAM2MM_GALS>; |
| clock-names = "cam", "cam-0", "cam-1", "cam-2", |
| "cam-3"; |
| mediatek,infracfg = <&infracfg>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| #power-domain-cells = <1>; |
| |
| power-domain@MT8192_POWER_DOMAIN_CAM_RAWA { |
| reg = <MT8192_POWER_DOMAIN_CAM_RAWA>; |
| clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>; |
| clock-names = "cam_rawa-0"; |
| #power-domain-cells = <0>; |
| }; |
| |
| power-domain@MT8192_POWER_DOMAIN_CAM_RAWB { |
| reg = <MT8192_POWER_DOMAIN_CAM_RAWB>; |
| clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>; |
| clock-names = "cam_rawb-0"; |
| #power-domain-cells = <0>; |
| }; |
| |
| power-domain@MT8192_POWER_DOMAIN_CAM_RAWC { |
| reg = <MT8192_POWER_DOMAIN_CAM_RAWC>; |
| clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>; |
| clock-names = "cam_rawc-0"; |
| #power-domain-cells = <0>; |
| }; |
| }; |
| }; |
| }; |
| }; |
| |
| watchdog: watchdog@10007000 { |
| compatible = "mediatek,mt8192-wdt"; |
| reg = <0 0x10007000 0 0x100>; |
| #reset-cells = <1>; |
| }; |
| |
| apmixedsys: syscon@1000c000 { |
| compatible = "mediatek,mt8192-apmixedsys", "syscon"; |
| reg = <0 0x1000c000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| systimer: timer@10017000 { |
| compatible = "mediatek,mt8192-timer", |
| "mediatek,mt6765-timer"; |
| reg = <0 0x10017000 0 0x1000>; |
| interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&topckgen CLK_TOP_CSW_F26M_D2>; |
| clock-names = "clk13m"; |
| }; |
| |
| pwrap: pwrap@10026000 { |
| compatible = "mediatek,mt6873-pwrap"; |
| reg = <0 0x10026000 0 0x1000>; |
| reg-names = "pwrap"; |
| interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&infracfg CLK_INFRA_PMIC_AP>, |
| <&infracfg CLK_INFRA_PMIC_TMR>; |
| clock-names = "spi", "wrap"; |
| assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>; |
| assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>; |
| }; |
| |
| spmi: spmi@10027000 { |
| compatible = "mediatek,mt6873-spmi"; |
| reg = <0 0x10027000 0 0x000e00>, |
| <0 0x10029000 0 0x000100>; |
| reg-names = "pmif", "spmimst"; |
| clocks = <&infracfg CLK_INFRA_PMIC_AP>, |
| <&infracfg CLK_INFRA_PMIC_TMR>, |
| <&topckgen CLK_TOP_SPMI_MST_SEL>; |
| clock-names = "pmif_sys_ck", |
| "pmif_tmr_ck", |
| "spmimst_clk_mux"; |
| assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>; |
| assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>; |
| }; |
| |
| gce: mailbox@10228000 { |
| compatible = "mediatek,mt8192-gce"; |
| reg = <0 0x10228000 0 0x4000>; |
| interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>; |
| #mbox-cells = <2>; |
| clocks = <&infracfg CLK_INFRA_GCE>; |
| clock-names = "gce"; |
| }; |
| |
| scp_adsp: clock-controller@10720000 { |
| compatible = "mediatek,mt8192-scp_adsp"; |
| reg = <0 0x10720000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| uart0: serial@11002000 { |
| compatible = "mediatek,mt8192-uart", |
| "mediatek,mt6577-uart"; |
| reg = <0 0x11002000 0 0x1000>; |
| interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; |
| clock-names = "baud", "bus"; |
| status = "disabled"; |
| }; |
| |
| uart1: serial@11003000 { |
| compatible = "mediatek,mt8192-uart", |
| "mediatek,mt6577-uart"; |
| reg = <0 0x11003000 0 0x1000>; |
| interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>; |
| clock-names = "baud", "bus"; |
| status = "disabled"; |
| }; |
| |
| imp_iic_wrap_c: clock-controller@11007000 { |
| compatible = "mediatek,mt8192-imp_iic_wrap_c"; |
| reg = <0 0x11007000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| spi0: spi@1100a000 { |
| compatible = "mediatek,mt8192-spi", |
| "mediatek,mt6765-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0 0x1100a000 0 0x1000>; |
| interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, |
| <&topckgen CLK_TOP_SPI_SEL>, |
| <&infracfg CLK_INFRA_SPI0>; |
| clock-names = "parent-clk", "sel-clk", "spi-clk"; |
| status = "disabled"; |
| }; |
| |
| pwm0: pwm@1100e000 { |
| compatible = "mediatek,mt8183-disp-pwm"; |
| reg = <0 0x1100e000 0 0x1000>; |
| interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>; |
| #pwm-cells = <2>; |
| clocks = <&topckgen CLK_TOP_DISP_PWM_SEL>, |
| <&infracfg CLK_INFRA_DISP_PWM>; |
| clock-names = "main", "mm"; |
| status = "disabled"; |
| }; |
| |
| spi1: spi@11010000 { |
| compatible = "mediatek,mt8192-spi", |
| "mediatek,mt6765-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0 0x11010000 0 0x1000>; |
| interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, |
| <&topckgen CLK_TOP_SPI_SEL>, |
| <&infracfg CLK_INFRA_SPI1>; |
| clock-names = "parent-clk", "sel-clk", "spi-clk"; |
| status = "disabled"; |
| }; |
| |
| spi2: spi@11012000 { |
| compatible = "mediatek,mt8192-spi", |
| "mediatek,mt6765-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0 0x11012000 0 0x1000>; |
| interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, |
| <&topckgen CLK_TOP_SPI_SEL>, |
| <&infracfg CLK_INFRA_SPI2>; |
| clock-names = "parent-clk", "sel-clk", "spi-clk"; |
| status = "disabled"; |
| }; |
| |
| spi3: spi@11013000 { |
| compatible = "mediatek,mt8192-spi", |
| "mediatek,mt6765-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0 0x11013000 0 0x1000>; |
| interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, |
| <&topckgen CLK_TOP_SPI_SEL>, |
| <&infracfg CLK_INFRA_SPI3>; |
| clock-names = "parent-clk", "sel-clk", "spi-clk"; |
| status = "disabled"; |
| }; |
| |
| spi4: spi@11018000 { |
| compatible = "mediatek,mt8192-spi", |
| "mediatek,mt6765-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0 0x11018000 0 0x1000>; |
| interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, |
| <&topckgen CLK_TOP_SPI_SEL>, |
| <&infracfg CLK_INFRA_SPI4>; |
| clock-names = "parent-clk", "sel-clk", "spi-clk"; |
| status = "disabled"; |
| }; |
| |
| spi5: spi@11019000 { |
| compatible = "mediatek,mt8192-spi", |
| "mediatek,mt6765-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0 0x11019000 0 0x1000>; |
| interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, |
| <&topckgen CLK_TOP_SPI_SEL>, |
| <&infracfg CLK_INFRA_SPI5>; |
| clock-names = "parent-clk", "sel-clk", "spi-clk"; |
| status = "disabled"; |
| }; |
| |
| spi6: spi@1101d000 { |
| compatible = "mediatek,mt8192-spi", |
| "mediatek,mt6765-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0 0x1101d000 0 0x1000>; |
| interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, |
| <&topckgen CLK_TOP_SPI_SEL>, |
| <&infracfg CLK_INFRA_SPI6>; |
| clock-names = "parent-clk", "sel-clk", "spi-clk"; |
| status = "disabled"; |
| }; |
| |
| spi7: spi@1101e000 { |
| compatible = "mediatek,mt8192-spi", |
| "mediatek,mt6765-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0 0x1101e000 0 0x1000>; |
| interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, |
| <&topckgen CLK_TOP_SPI_SEL>, |
| <&infracfg CLK_INFRA_SPI7>; |
| clock-names = "parent-clk", "sel-clk", "spi-clk"; |
| status = "disabled"; |
| }; |
| |
| scp: scp@10500000 { |
| compatible = "mediatek,mt8192-scp"; |
| reg = <0 0x10500000 0 0x100000>, |
| <0 0x10720000 0 0xe0000>, |
| <0 0x10700000 0 0x8000>; |
| reg-names = "sram", "cfg", "l1tcm"; |
| interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&infracfg CLK_INFRA_SCPSYS>; |
| clock-names = "main"; |
| status = "disabled"; |
| }; |
| |
| xhci: usb@11200000 { |
| compatible = "mediatek,mt8192-xhci", |
| "mediatek,mtk-xhci"; |
| reg = <0 0x11200000 0 0x1000>, |
| <0 0x11203e00 0 0x0100>; |
| reg-names = "mac", "ippc"; |
| interrupts-extended = <&gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>; |
| interrupt-names = "host"; |
| phys = <&u2port0 PHY_TYPE_USB2>, |
| <&u3port0 PHY_TYPE_USB3>; |
| assigned-clocks = <&topckgen CLK_TOP_USB_TOP_SEL>, |
| <&topckgen CLK_TOP_SSUSB_XHCI_SEL>; |
| assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, |
| <&topckgen CLK_TOP_UNIVPLL_D5_D4>; |
| clocks = <&infracfg CLK_INFRA_SSUSB>, |
| <&apmixedsys CLK_APMIXED_USBPLL>, |
| <&clk26m>, |
| <&clk26m>, |
| <&infracfg CLK_INFRA_SSUSB_XHCI>; |
| clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", |
| "xhci_ck"; |
| wakeup-source; |
| mediatek,syscon-wakeup = <&pericfg 0x420 102>; |
| status = "disabled"; |
| }; |
| |
| audsys: syscon@11210000 { |
| compatible = "mediatek,mt8192-audsys", "syscon"; |
| reg = <0 0x11210000 0 0x2000>; |
| #clock-cells = <1>; |
| |
| afe: mt8192-afe-pcm { |
| compatible = "mediatek,mt8192-audio"; |
| interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 0>; |
| resets = <&watchdog 17>; |
| reset-names = "audiosys"; |
| mediatek,apmixedsys = <&apmixedsys>; |
| mediatek,infracfg = <&infracfg>; |
| mediatek,topckgen = <&topckgen>; |
| power-domains = <&spm MT8192_POWER_DOMAIN_AUDIO>; |
| clocks = <&audsys CLK_AUD_AFE>, |
| <&audsys CLK_AUD_DAC>, |
| <&audsys CLK_AUD_DAC_PREDIS>, |
| <&audsys CLK_AUD_ADC>, |
| <&audsys CLK_AUD_ADDA6_ADC>, |
| <&audsys CLK_AUD_22M>, |
| <&audsys CLK_AUD_24M>, |
| <&audsys CLK_AUD_APLL_TUNER>, |
| <&audsys CLK_AUD_APLL2_TUNER>, |
| <&audsys CLK_AUD_TDM>, |
| <&audsys CLK_AUD_TML>, |
| <&audsys CLK_AUD_NLE>, |
| <&audsys CLK_AUD_DAC_HIRES>, |
| <&audsys CLK_AUD_ADC_HIRES>, |
| <&audsys CLK_AUD_ADC_HIRES_TML>, |
| <&audsys CLK_AUD_ADDA6_ADC_HIRES>, |
| <&audsys CLK_AUD_3RD_DAC>, |
| <&audsys CLK_AUD_3RD_DAC_PREDIS>, |
| <&audsys CLK_AUD_3RD_DAC_TML>, |
| <&audsys CLK_AUD_3RD_DAC_HIRES>, |
| <&infracfg CLK_INFRA_AUDIO>, |
| <&infracfg CLK_INFRA_AUDIO_26M_B>, |
| <&topckgen CLK_TOP_AUDIO_SEL>, |
| <&topckgen CLK_TOP_AUD_INTBUS_SEL>, |
| <&topckgen CLK_TOP_MAINPLL_D4_D4>, |
| <&topckgen CLK_TOP_AUD_1_SEL>, |
| <&topckgen CLK_TOP_APLL1>, |
| <&topckgen CLK_TOP_AUD_2_SEL>, |
| <&topckgen CLK_TOP_APLL2>, |
| <&topckgen CLK_TOP_AUD_ENGEN1_SEL>, |
| <&topckgen CLK_TOP_APLL1_D4>, |
| <&topckgen CLK_TOP_AUD_ENGEN2_SEL>, |
| <&topckgen CLK_TOP_APLL2_D4>, |
| <&topckgen CLK_TOP_APLL_I2S0_M_SEL>, |
| <&topckgen CLK_TOP_APLL_I2S1_M_SEL>, |
| <&topckgen CLK_TOP_APLL_I2S2_M_SEL>, |
| <&topckgen CLK_TOP_APLL_I2S3_M_SEL>, |
| <&topckgen CLK_TOP_APLL_I2S4_M_SEL>, |
| <&topckgen CLK_TOP_APLL_I2S5_M_SEL>, |
| <&topckgen CLK_TOP_APLL_I2S6_M_SEL>, |
| <&topckgen CLK_TOP_APLL_I2S7_M_SEL>, |
| <&topckgen CLK_TOP_APLL_I2S8_M_SEL>, |
| <&topckgen CLK_TOP_APLL_I2S9_M_SEL>, |
| <&topckgen CLK_TOP_APLL12_DIV0>, |
| <&topckgen CLK_TOP_APLL12_DIV1>, |
| <&topckgen CLK_TOP_APLL12_DIV2>, |
| <&topckgen CLK_TOP_APLL12_DIV3>, |
| <&topckgen CLK_TOP_APLL12_DIV4>, |
| <&topckgen CLK_TOP_APLL12_DIVB>, |
| <&topckgen CLK_TOP_APLL12_DIV5>, |
| <&topckgen CLK_TOP_APLL12_DIV6>, |
| <&topckgen CLK_TOP_APLL12_DIV7>, |
| <&topckgen CLK_TOP_APLL12_DIV8>, |
| <&topckgen CLK_TOP_APLL12_DIV9>, |
| <&topckgen CLK_TOP_AUDIO_H_SEL>, |
| <&clk26m>; |
| clock-names = "aud_afe_clk", |
| "aud_dac_clk", |
| "aud_dac_predis_clk", |
| "aud_adc_clk", |
| "aud_adda6_adc_clk", |
| "aud_apll22m_clk", |
| "aud_apll24m_clk", |
| "aud_apll1_tuner_clk", |
| "aud_apll2_tuner_clk", |
| "aud_tdm_clk", |
| "aud_tml_clk", |
| "aud_nle", |
| "aud_dac_hires_clk", |
| "aud_adc_hires_clk", |
| "aud_adc_hires_tml", |
| "aud_adda6_adc_hires_clk", |
| "aud_3rd_dac_clk", |
| "aud_3rd_dac_predis_clk", |
| "aud_3rd_dac_tml", |
| "aud_3rd_dac_hires_clk", |
| "aud_infra_clk", |
| "aud_infra_26m_clk", |
| "top_mux_audio", |
| "top_mux_audio_int", |
| "top_mainpll_d4_d4", |
| "top_mux_aud_1", |
| "top_apll1_ck", |
| "top_mux_aud_2", |
| "top_apll2_ck", |
| "top_mux_aud_eng1", |
| "top_apll1_d4", |
| "top_mux_aud_eng2", |
| "top_apll2_d4", |
| "top_i2s0_m_sel", |
| "top_i2s1_m_sel", |
| "top_i2s2_m_sel", |
| "top_i2s3_m_sel", |
| "top_i2s4_m_sel", |
| "top_i2s5_m_sel", |
| "top_i2s6_m_sel", |
| "top_i2s7_m_sel", |
| "top_i2s8_m_sel", |
| "top_i2s9_m_sel", |
| "top_apll12_div0", |
| "top_apll12_div1", |
| "top_apll12_div2", |
| "top_apll12_div3", |
| "top_apll12_div4", |
| "top_apll12_divb", |
| "top_apll12_div5", |
| "top_apll12_div6", |
| "top_apll12_div7", |
| "top_apll12_div8", |
| "top_apll12_div9", |
| "top_mux_audio_h", |
| "top_clk26m_clk"; |
| }; |
| }; |
| |
| pcie: pcie@11230000 { |
| compatible = "mediatek,mt8192-pcie"; |
| device_type = "pci"; |
| reg = <0 0x11230000 0 0x2000>; |
| reg-names = "pcie-mac"; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| clocks = <&infracfg CLK_INFRA_PCIE_PL_P_250M>, |
| <&infracfg CLK_INFRA_PCIE_TL_26M>, |
| <&infracfg CLK_INFRA_PCIE_TL_96M>, |
| <&infracfg CLK_INFRA_PCIE_TL_32K>, |
| <&infracfg CLK_INFRA_PCIE_PERI_26M>, |
| <&infracfg CLK_INFRA_PCIE_TOP_H_133M>; |
| clock-names = "pl_250m", "tl_26m", "tl_96m", |
| "tl_32k", "peri_26m", "top_133m"; |
| assigned-clocks = <&topckgen CLK_TOP_TL_SEL>; |
| assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D6_D4>; |
| interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>; |
| bus-range = <0x00 0xff>; |
| ranges = <0x82000000 0 0x12000000 0x0 0x12000000 0 0x0800000>, |
| <0x81000000 0 0x12800000 0x0 0x12800000 0 0x0800000>; |
| #interrupt-cells = <1>; |
| interrupt-map-mask = <0 0 0 7>; |
| interrupt-map = <0 0 0 1 &pcie_intc0 0>, |
| <0 0 0 2 &pcie_intc0 1>, |
| <0 0 0 3 &pcie_intc0 2>, |
| <0 0 0 4 &pcie_intc0 3>; |
| |
| pcie_intc0: interrupt-controller { |
| interrupt-controller; |
| #address-cells = <0>; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| nor_flash: spi@11234000 { |
| compatible = "mediatek,mt8192-nor"; |
| reg = <0 0x11234000 0 0xe0>; |
| interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&topckgen CLK_TOP_SFLASH_SEL>, |
| <&infracfg CLK_INFRA_FLASHIF_SFLASH>, |
| <&infracfg CLK_INFRA_FLASHIF_TOP_H_133M>; |
| clock-names = "spi", "sf", "axi"; |
| assigned-clocks = <&topckgen CLK_TOP_SFLASH_SEL>; |
| assigned-clock-parents = <&clk26m>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| efuse: efuse@11c10000 { |
| compatible = "mediatek,mt8192-efuse", "mediatek,efuse"; |
| reg = <0 0x11c10000 0 0x1000>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| lvts_e_data1: data1@1c0 { |
| reg = <0x1c0 0x58>; |
| }; |
| |
| svs_calibration: calib@580 { |
| reg = <0x580 0x68>; |
| }; |
| }; |
| |
| i2c3: i2c@11cb0000 { |
| compatible = "mediatek,mt8192-i2c"; |
| reg = <0 0x11cb0000 0 0x1000>, |
| <0 0x10217300 0 0x80>; |
| interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&imp_iic_wrap_e CLK_IMP_IIC_WRAP_E_I2C3>, |
| <&infracfg CLK_INFRA_AP_DMA>; |
| clock-names = "main", "dma"; |
| clock-div = <1>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| imp_iic_wrap_e: clock-controller@11cb1000 { |
| compatible = "mediatek,mt8192-imp_iic_wrap_e"; |
| reg = <0 0x11cb1000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| i2c7: i2c@11d00000 { |
| compatible = "mediatek,mt8192-i2c"; |
| reg = <0 0x11d00000 0 0x1000>, |
| <0 0x10217600 0 0x180>; |
| interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>, |
| <&infracfg CLK_INFRA_AP_DMA>; |
| clock-names = "main", "dma"; |
| clock-div = <1>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c8: i2c@11d01000 { |
| compatible = "mediatek,mt8192-i2c"; |
| reg = <0 0x11d01000 0 0x1000>, |
| <0 0x10217780 0 0x180>; |
| interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C8>, |
| <&infracfg CLK_INFRA_AP_DMA>; |
| clock-names = "main", "dma"; |
| clock-div = <1>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c9: i2c@11d02000 { |
| compatible = "mediatek,mt8192-i2c"; |
| reg = <0 0x11d02000 0 0x1000>, |
| <0 0x10217900 0 0x180>; |
| interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C9>, |
| <&infracfg CLK_INFRA_AP_DMA>; |
| clock-names = "main", "dma"; |
| clock-div = <1>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| imp_iic_wrap_s: clock-controller@11d03000 { |
| compatible = "mediatek,mt8192-imp_iic_wrap_s"; |
| reg = <0 0x11d03000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| i2c1: i2c@11d20000 { |
| compatible = "mediatek,mt8192-i2c"; |
| reg = <0 0x11d20000 0 0x1000>, |
| <0 0x10217100 0 0x80>; |
| interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C1>, |
| <&infracfg CLK_INFRA_AP_DMA>; |
| clock-names = "main", "dma"; |
| clock-div = <1>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c2: i2c@11d21000 { |
| compatible = "mediatek,mt8192-i2c"; |
| reg = <0 0x11d21000 0 0x1000>, |
| <0 0x10217180 0 0x180>; |
| interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C2>, |
| <&infracfg CLK_INFRA_AP_DMA>; |
| clock-names = "main", "dma"; |
| clock-div = <1>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c4: i2c@11d22000 { |
| compatible = "mediatek,mt8192-i2c"; |
| reg = <0 0x11d22000 0 0x1000>, |
| <0 0x10217380 0 0x180>; |
| interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C4>, |
| <&infracfg CLK_INFRA_AP_DMA>; |
| clock-names = "main", "dma"; |
| clock-div = <1>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| imp_iic_wrap_ws: clock-controller@11d23000 { |
| compatible = "mediatek,mt8192-imp_iic_wrap_ws"; |
| reg = <0 0x11d23000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| i2c5: i2c@11e00000 { |
| compatible = "mediatek,mt8192-i2c"; |
| reg = <0 0x11e00000 0 0x1000>, |
| <0 0x10217500 0 0x80>; |
| interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C5>, |
| <&infracfg CLK_INFRA_AP_DMA>; |
| clock-names = "main", "dma"; |
| clock-div = <1>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| imp_iic_wrap_w: clock-controller@11e01000 { |
| compatible = "mediatek,mt8192-imp_iic_wrap_w"; |
| reg = <0 0x11e01000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| u3phy0: t-phy@11e40000 { |
| compatible = "mediatek,mt8192-tphy", |
| "mediatek,generic-tphy-v2"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x0 0x11e40000 0x1000>; |
| |
| u2port0: usb-phy@0 { |
| reg = <0x0 0x700>; |
| clocks = <&clk26m>; |
| clock-names = "ref"; |
| #phy-cells = <1>; |
| }; |
| |
| u3port0: usb-phy@700 { |
| reg = <0x700 0x900>; |
| clocks = <&clk26m>; |
| clock-names = "ref"; |
| #phy-cells = <1>; |
| }; |
| }; |
| |
| mipi_tx0: dsi-phy@11e50000 { |
| compatible = "mediatek,mt8183-mipi-tx"; |
| reg = <0 0x11e50000 0 0x1000>; |
| clocks = <&apmixedsys CLK_APMIXED_MIPID26M>; |
| #clock-cells = <0>; |
| #phy-cells = <0>; |
| clock-output-names = "mipi_tx0_pll"; |
| status = "disabled"; |
| }; |
| |
| i2c0: i2c@11f00000 { |
| compatible = "mediatek,mt8192-i2c"; |
| reg = <0 0x11f00000 0 0x1000>, |
| <0 0x10217080 0 0x80>; |
| interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C0>, |
| <&infracfg CLK_INFRA_AP_DMA>; |
| clock-names = "main", "dma"; |
| clock-div = <1>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c6: i2c@11f01000 { |
| compatible = "mediatek,mt8192-i2c"; |
| reg = <0 0x11f01000 0 0x1000>, |
| <0 0x10217580 0 0x80>; |
| interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C6>, |
| <&infracfg CLK_INFRA_AP_DMA>; |
| clock-names = "main", "dma"; |
| clock-div = <1>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| imp_iic_wrap_n: clock-controller@11f02000 { |
| compatible = "mediatek,mt8192-imp_iic_wrap_n"; |
| reg = <0 0x11f02000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| msdc_top: clock-controller@11f10000 { |
| compatible = "mediatek,mt8192-msdc_top"; |
| reg = <0 0x11f10000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| mmc0: mmc@11f60000 { |
| compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc"; |
| reg = <0 0x11f60000 0 0x1000>, <0 0x11f50000 0 0x1000>; |
| interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>, |
| <&msdc_top CLK_MSDC_TOP_H_MST_0P>, |
| <&msdc_top CLK_MSDC_TOP_SRC_0P>, |
| <&msdc_top CLK_MSDC_TOP_P_CFG>, |
| <&msdc_top CLK_MSDC_TOP_P_MSDC0>, |
| <&msdc_top CLK_MSDC_TOP_AXI>, |
| <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>; |
| clock-names = "source", "hclk", "source_cg", "sys_cg", |
| "pclk_cg", "axi_cg", "ahb_cg"; |
| status = "disabled"; |
| }; |
| |
| mmc1: mmc@11f70000 { |
| compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc"; |
| reg = <0 0x11f70000 0 0x1000>, <0 0x11c70000 0 0x1000>; |
| interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>, |
| <&msdc_top CLK_MSDC_TOP_H_MST_1P>, |
| <&msdc_top CLK_MSDC_TOP_SRC_1P>, |
| <&msdc_top CLK_MSDC_TOP_P_CFG>, |
| <&msdc_top CLK_MSDC_TOP_P_MSDC1>, |
| <&msdc_top CLK_MSDC_TOP_AXI>, |
| <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>; |
| clock-names = "source", "hclk", "source_cg", "sys_cg", |
| "pclk_cg", "axi_cg", "ahb_cg"; |
| status = "disabled"; |
| }; |
| |
| mfgcfg: clock-controller@13fbf000 { |
| compatible = "mediatek,mt8192-mfgcfg"; |
| reg = <0 0x13fbf000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| mmsys: syscon@14000000 { |
| compatible = "mediatek,mt8192-mmsys", "syscon"; |
| reg = <0 0x14000000 0 0x1000>; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, |
| <&gce 1 CMDQ_THR_PRIO_HIGHEST>; |
| mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; |
| }; |
| |
| mutex: mutex@14001000 { |
| compatible = "mediatek,mt8192-disp-mutex"; |
| reg = <0 0x14001000 0 0x1000>; |
| interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&mmsys CLK_MM_DISP_MUTEX0>; |
| mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>, |
| <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>; |
| power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; |
| }; |
| |
| smi_common: smi@14002000 { |
| compatible = "mediatek,mt8192-smi-common"; |
| reg = <0 0x14002000 0 0x1000>; |
| clocks = <&mmsys CLK_MM_SMI_COMMON>, |
| <&mmsys CLK_MM_SMI_INFRA>, |
| <&mmsys CLK_MM_SMI_GALS>, |
| <&mmsys CLK_MM_SMI_GALS>; |
| clock-names = "apb", "smi", "gals0", "gals1"; |
| power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; |
| }; |
| |
| larb0: larb@14003000 { |
| compatible = "mediatek,mt8192-smi-larb"; |
| reg = <0 0x14003000 0 0x1000>; |
| mediatek,larb-id = <0>; |
| mediatek,smi = <&smi_common>; |
| clocks = <&clk26m>, <&clk26m>; |
| clock-names = "apb", "smi"; |
| power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; |
| }; |
| |
| larb1: larb@14004000 { |
| compatible = "mediatek,mt8192-smi-larb"; |
| reg = <0 0x14004000 0 0x1000>; |
| mediatek,larb-id = <1>; |
| mediatek,smi = <&smi_common>; |
| clocks = <&clk26m>, <&clk26m>; |
| clock-names = "apb", "smi"; |
| power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; |
| }; |
| |
| ovl0: ovl@14005000 { |
| compatible = "mediatek,mt8192-disp-ovl"; |
| reg = <0 0x14005000 0 0x1000>; |
| interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&mmsys CLK_MM_DISP_OVL0>; |
| iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>, |
| <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>; |
| power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; |
| mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>; |
| }; |
| |
| ovl_2l0: ovl@14006000 { |
| compatible = "mediatek,mt8192-disp-ovl-2l"; |
| reg = <0 0x14006000 0 0x1000>; |
| interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>; |
| power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; |
| clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; |
| iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>, |
| <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>; |
| mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>; |
| }; |
| |
| rdma0: rdma@14007000 { |
| compatible = "mediatek,mt8192-disp-rdma", |
| "mediatek,mt8183-disp-rdma"; |
| reg = <0 0x14007000 0 0x1000>; |
| interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&mmsys CLK_MM_DISP_RDMA0>; |
| iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>; |
| mediatek,rdma-fifo-size = <5120>; |
| power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; |
| mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>; |
| }; |
| |
| color0: color@14009000 { |
| compatible = "mediatek,mt8192-disp-color", |
| "mediatek,mt8173-disp-color"; |
| reg = <0 0x14009000 0 0x1000>; |
| interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>; |
| power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; |
| clocks = <&mmsys CLK_MM_DISP_COLOR0>; |
| mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>; |
| }; |
| |
| ccorr0: ccorr@1400a000 { |
| compatible = "mediatek,mt8192-disp-ccorr"; |
| reg = <0 0x1400a000 0 0x1000>; |
| interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>; |
| power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; |
| clocks = <&mmsys CLK_MM_DISP_CCORR0>; |
| mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>; |
| }; |
| |
| aal0: aal@1400b000 { |
| compatible = "mediatek,mt8192-disp-aal", |
| "mediatek,mt8183-disp-aal"; |
| reg = <0 0x1400b000 0 0x1000>; |
| interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>; |
| power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; |
| clocks = <&mmsys CLK_MM_DISP_AAL0>; |
| mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>; |
| }; |
| |
| gamma0: gamma@1400c000 { |
| compatible = "mediatek,mt8192-disp-gamma", |
| "mediatek,mt8183-disp-gamma"; |
| reg = <0 0x1400c000 0 0x1000>; |
| interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>; |
| power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; |
| clocks = <&mmsys CLK_MM_DISP_GAMMA0>; |
| mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; |
| }; |
| |
| postmask0: postmask@1400d000 { |
| compatible = "mediatek,mt8192-disp-postmask"; |
| reg = <0 0x1400d000 0 0x1000>; |
| interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>; |
| power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; |
| clocks = <&mmsys CLK_MM_DISP_POSTMASK0>; |
| mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>; |
| }; |
| |
| dither0: dither@1400e000 { |
| compatible = "mediatek,mt8192-disp-dither", |
| "mediatek,mt8183-disp-dither"; |
| reg = <0 0x1400e000 0 0x1000>; |
| interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>; |
| power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; |
| clocks = <&mmsys CLK_MM_DISP_DITHER0>; |
| mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; |
| }; |
| |
| dsi0: dsi@14010000 { |
| compatible = "mediatek,mt8183-dsi"; |
| reg = <0 0x14010000 0 0x1000>; |
| interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&mmsys CLK_MM_DSI0>, |
| <&mmsys CLK_MM_DSI_DSI0>, |
| <&mipi_tx0>; |
| clock-names = "engine", "digital", "hs"; |
| phys = <&mipi_tx0>; |
| phy-names = "dphy"; |
| power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; |
| resets = <&mmsys MT8192_MMSYS_SW0_RST_B_DISP_DSI0>; |
| status = "disabled"; |
| |
| port { |
| dsi_out: endpoint { }; |
| }; |
| }; |
| |
| ovl_2l2: ovl@14014000 { |
| compatible = "mediatek,mt8192-disp-ovl-2l"; |
| reg = <0 0x14014000 0 0x1000>; |
| interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH 0>; |
| power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; |
| clocks = <&mmsys CLK_MM_DISP_OVL2_2L>; |
| iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>, |
| <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>; |
| mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>; |
| }; |
| |
| rdma4: rdma@14015000 { |
| compatible = "mediatek,mt8192-disp-rdma", |
| "mediatek,mt8183-disp-rdma"; |
| reg = <0 0x14015000 0 0x1000>; |
| interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>; |
| power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; |
| clocks = <&mmsys CLK_MM_DISP_RDMA4>; |
| iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>; |
| mediatek,rdma-fifo-size = <2048>; |
| mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>; |
| }; |
| |
| dpi0: dpi@14016000 { |
| compatible = "mediatek,mt8192-dpi"; |
| reg = <0 0x14016000 0 0x1000>; |
| interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&mmsys CLK_MM_DPI_DPI0>, |
| <&mmsys CLK_MM_DISP_DPI0>, |
| <&apmixedsys CLK_APMIXED_TVDPLL>; |
| clock-names = "pixel", "engine", "pll"; |
| status = "disabled"; |
| }; |
| |
| iommu0: m4u@1401d000 { |
| compatible = "mediatek,mt8192-m4u"; |
| reg = <0 0x1401d000 0 0x1000>; |
| mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, |
| <&larb4>, <&larb5>, <&larb7>, |
| <&larb9>, <&larb11>, <&larb13>, |
| <&larb14>, <&larb16>, <&larb17>, |
| <&larb18>, <&larb19>, <&larb20>; |
| interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&mmsys CLK_MM_SMI_IOMMU>; |
| clock-names = "bclk"; |
| power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; |
| #iommu-cells = <1>; |
| }; |
| |
| imgsys: clock-controller@15020000 { |
| compatible = "mediatek,mt8192-imgsys"; |
| reg = <0 0x15020000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| larb9: larb@1502e000 { |
| compatible = "mediatek,mt8192-smi-larb"; |
| reg = <0 0x1502e000 0 0x1000>; |
| mediatek,larb-id = <9>; |
| mediatek,smi = <&smi_common>; |
| clocks = <&imgsys CLK_IMG_LARB9>, |
| <&imgsys CLK_IMG_LARB9>; |
| clock-names = "apb", "smi"; |
| power-domains = <&spm MT8192_POWER_DOMAIN_ISP>; |
| }; |
| |
| imgsys2: clock-controller@15820000 { |
| compatible = "mediatek,mt8192-imgsys2"; |
| reg = <0 0x15820000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| larb11: larb@1582e000 { |
| compatible = "mediatek,mt8192-smi-larb"; |
| reg = <0 0x1582e000 0 0x1000>; |
| mediatek,larb-id = <11>; |
| mediatek,smi = <&smi_common>; |
| clocks = <&imgsys2 CLK_IMG2_LARB11>, |
| <&imgsys2 CLK_IMG2_LARB11>; |
| clock-names = "apb", "smi"; |
| power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>; |
| }; |
| |
| larb5: larb@1600d000 { |
| compatible = "mediatek,mt8192-smi-larb"; |
| reg = <0 0x1600d000 0 0x1000>; |
| mediatek,larb-id = <5>; |
| mediatek,smi = <&smi_common>; |
| clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>, |
| <&vdecsys_soc CLK_VDEC_SOC_LARB1>; |
| clock-names = "apb", "smi"; |
| power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>; |
| }; |
| |
| vdecsys_soc: clock-controller@1600f000 { |
| compatible = "mediatek,mt8192-vdecsys_soc"; |
| reg = <0 0x1600f000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| larb4: larb@1602e000 { |
| compatible = "mediatek,mt8192-smi-larb"; |
| reg = <0 0x1602e000 0 0x1000>; |
| mediatek,larb-id = <4>; |
| mediatek,smi = <&smi_common>; |
| clocks = <&vdecsys CLK_VDEC_SOC_LARB1>, |
| <&vdecsys CLK_VDEC_SOC_LARB1>; |
| clock-names = "apb", "smi"; |
| power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>; |
| }; |
| |
| vdecsys: clock-controller@1602f000 { |
| compatible = "mediatek,mt8192-vdecsys"; |
| reg = <0 0x1602f000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| vencsys: clock-controller@17000000 { |
| compatible = "mediatek,mt8192-vencsys"; |
| reg = <0 0x17000000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| larb7: larb@17010000 { |
| compatible = "mediatek,mt8192-smi-larb"; |
| reg = <0 0x17010000 0 0x1000>; |
| mediatek,larb-id = <7>; |
| mediatek,smi = <&smi_common>; |
| clocks = <&vencsys CLK_VENC_SET0_LARB>, |
| <&vencsys CLK_VENC_SET1_VENC>; |
| clock-names = "apb", "smi"; |
| power-domains = <&spm MT8192_POWER_DOMAIN_VENC>; |
| }; |
| |
| vcodec_enc: vcodec@17020000 { |
| compatible = "mediatek,mt8192-vcodec-enc"; |
| reg = <0 0x17020000 0 0x2000>; |
| iommus = <&iommu0 M4U_PORT_L7_VENC_RCPU>, |
| <&iommu0 M4U_PORT_L7_VENC_REC>, |
| <&iommu0 M4U_PORT_L7_VENC_BSDMA>, |
| <&iommu0 M4U_PORT_L7_VENC_SV_COMV>, |
| <&iommu0 M4U_PORT_L7_VENC_RD_COMV>, |
| <&iommu0 M4U_PORT_L7_VENC_CUR_LUMA>, |
| <&iommu0 M4U_PORT_L7_VENC_CUR_CHROMA>, |
| <&iommu0 M4U_PORT_L7_VENC_REF_LUMA>, |
| <&iommu0 M4U_PORT_L7_VENC_REF_CHROMA>, |
| <&iommu0 M4U_PORT_L7_VENC_SUB_R_LUMA>, |
| <&iommu0 M4U_PORT_L7_VENC_SUB_W_LUMA>; |
| interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 0>; |
| mediatek,scp = <&scp>; |
| power-domains = <&spm MT8192_POWER_DOMAIN_VENC>; |
| clocks = <&vencsys CLK_VENC_SET1_VENC>; |
| clock-names = "venc-set1"; |
| assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>; |
| assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; |
| }; |
| |
| camsys: clock-controller@1a000000 { |
| compatible = "mediatek,mt8192-camsys"; |
| reg = <0 0x1a000000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| larb13: larb@1a001000 { |
| compatible = "mediatek,mt8192-smi-larb"; |
| reg = <0 0x1a001000 0 0x1000>; |
| mediatek,larb-id = <13>; |
| mediatek,smi = <&smi_common>; |
| clocks = <&camsys CLK_CAM_CAM>, |
| <&camsys CLK_CAM_LARB13>; |
| clock-names = "apb", "smi"; |
| power-domains = <&spm MT8192_POWER_DOMAIN_CAM>; |
| }; |
| |
| larb14: larb@1a002000 { |
| compatible = "mediatek,mt8192-smi-larb"; |
| reg = <0 0x1a002000 0 0x1000>; |
| mediatek,larb-id = <14>; |
| mediatek,smi = <&smi_common>; |
| clocks = <&camsys CLK_CAM_CAM>, |
| <&camsys CLK_CAM_LARB14>; |
| clock-names = "apb", "smi"; |
| power-domains = <&spm MT8192_POWER_DOMAIN_CAM>; |
| }; |
| |
| larb16: larb@1a00f000 { |
| compatible = "mediatek,mt8192-smi-larb"; |
| reg = <0 0x1a00f000 0 0x1000>; |
| mediatek,larb-id = <16>; |
| mediatek,smi = <&smi_common>; |
| clocks = <&camsys_rawa CLK_CAM_RAWA_CAM>, |
| <&camsys_rawa CLK_CAM_RAWA_LARBX>; |
| clock-names = "apb", "smi"; |
| power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWA>; |
| }; |
| |
| larb17: larb@1a010000 { |
| compatible = "mediatek,mt8192-smi-larb"; |
| reg = <0 0x1a010000 0 0x1000>; |
| mediatek,larb-id = <17>; |
| mediatek,smi = <&smi_common>; |
| clocks = <&camsys_rawb CLK_CAM_RAWB_CAM>, |
| <&camsys_rawb CLK_CAM_RAWB_LARBX>; |
| clock-names = "apb", "smi"; |
| power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWB>; |
| }; |
| |
| larb18: larb@1a011000 { |
| compatible = "mediatek,mt8192-smi-larb"; |
| reg = <0 0x1a011000 0 0x1000>; |
| mediatek,larb-id = <18>; |
| mediatek,smi = <&smi_common>; |
| clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>, |
| <&camsys_rawc CLK_CAM_RAWC_CAM>; |
| clock-names = "apb", "smi"; |
| power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWC>; |
| }; |
| |
| camsys_rawa: clock-controller@1a04f000 { |
| compatible = "mediatek,mt8192-camsys_rawa"; |
| reg = <0 0x1a04f000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| camsys_rawb: clock-controller@1a06f000 { |
| compatible = "mediatek,mt8192-camsys_rawb"; |
| reg = <0 0x1a06f000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| camsys_rawc: clock-controller@1a08f000 { |
| compatible = "mediatek,mt8192-camsys_rawc"; |
| reg = <0 0x1a08f000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| ipesys: clock-controller@1b000000 { |
| compatible = "mediatek,mt8192-ipesys"; |
| reg = <0 0x1b000000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| larb20: larb@1b00f000 { |
| compatible = "mediatek,mt8192-smi-larb"; |
| reg = <0 0x1b00f000 0 0x1000>; |
| mediatek,larb-id = <20>; |
| mediatek,smi = <&smi_common>; |
| clocks = <&ipesys CLK_IPE_SMI_SUBCOM>, |
| <&ipesys CLK_IPE_LARB20>; |
| clock-names = "apb", "smi"; |
| power-domains = <&spm MT8192_POWER_DOMAIN_IPE>; |
| }; |
| |
| larb19: larb@1b10f000 { |
| compatible = "mediatek,mt8192-smi-larb"; |
| reg = <0 0x1b10f000 0 0x1000>; |
| mediatek,larb-id = <19>; |
| mediatek,smi = <&smi_common>; |
| clocks = <&ipesys CLK_IPE_SMI_SUBCOM>, |
| <&ipesys CLK_IPE_LARB19>; |
| clock-names = "apb", "smi"; |
| power-domains = <&spm MT8192_POWER_DOMAIN_IPE>; |
| }; |
| |
| mdpsys: clock-controller@1f000000 { |
| compatible = "mediatek,mt8192-mdpsys"; |
| reg = <0 0x1f000000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| larb2: larb@1f002000 { |
| compatible = "mediatek,mt8192-smi-larb"; |
| reg = <0 0x1f002000 0 0x1000>; |
| mediatek,larb-id = <2>; |
| mediatek,smi = <&smi_common>; |
| clocks = <&mdpsys CLK_MDP_SMI0>, |
| <&mdpsys CLK_MDP_SMI0>; |
| clock-names = "apb", "smi"; |
| power-domains = <&spm MT8192_POWER_DOMAIN_MDP>; |
| }; |
| }; |
| }; |
