| # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) |
| %YAML 1.2 |
| --- |
| $id: http://devicetree.org/schemas/clock/sophgo,sg2042-clkgen.yaml# |
| $schema: http://devicetree.org/meta-schemas/core.yaml# |
| |
| title: Sophgo SG2042 Clock Generator for divider/mux/gate |
| |
| maintainers: |
| - Chen Wang <unicorn_wang@outlook.com> |
| |
| properties: |
| compatible: |
| const: sophgo,sg2042-clkgen |
| |
| reg: |
| maxItems: 1 |
| |
| clocks: |
| items: |
| - description: Main PLL |
| - description: Fixed PLL |
| - description: DDR PLL 0 |
| - description: DDR PLL 1 |
| |
| clock-names: |
| items: |
| - const: mpll |
| - const: fpll |
| - const: dpll0 |
| - const: dpll1 |
| |
| '#clock-cells': |
| const: 1 |
| description: |
| See <dt-bindings/clock/sophgo,sg2042-clkgen.h> for valid indices. |
| |
| required: |
| - compatible |
| - reg |
| - clocks |
| - clock-names |
| - '#clock-cells' |
| |
| additionalProperties: false |
| |
| examples: |
| - | |
| clock-controller@30012000 { |
| compatible = "sophgo,sg2042-clkgen"; |
| reg = <0x30012000 0x1000>; |
| clocks = <&pllclk 0>, |
| <&pllclk 1>, |
| <&pllclk 2>, |
| <&pllclk 3>; |
| clock-names = "mpll", |
| "fpll", |
| "dpll0", |
| "dpll1"; |
| #clock-cells = <1>; |
| }; |