| # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) |
| %YAML 1.2 |
| --- |
| $id: http://devicetree.org/schemas/mmc/arm,pl18x.yaml# |
| $schema: http://devicetree.org/meta-schemas/core.yaml# |
| |
| title: ARM PrimeCell MultiMedia Card Interface (MMCI) PL180 and PL181 |
| |
| maintainers: |
| - Linus Walleij <linus.walleij@linaro.org> |
| - Ulf Hansson <ulf.hansson@linaro.org> |
| |
| description: |
| The ARM PrimeCells MMCI PL180 and PL181 provides an interface for |
| reading and writing to MultiMedia and SD cards alike. Over the years |
| vendors have use the VHDL code from ARM to create derivative MMC/SD/SDIO |
| host controllers with very similar characteristics. |
| |
| allOf: |
| - $ref: /schemas/arm/primecell.yaml# |
| - $ref: mmc-controller.yaml# |
| |
| # We need a select here so we don't match all nodes with 'arm,primecell' |
| select: |
| properties: |
| compatible: |
| contains: |
| enum: |
| - arm,pl180 |
| - arm,pl181 |
| - arm,pl18x |
| required: |
| - compatible |
| |
| properties: |
| compatible: |
| oneOf: |
| - description: The first version of the block, simply called |
| PL180 and found in the ARM Integrator IM/PD1 logic module. |
| items: |
| - const: arm,pl180 |
| - const: arm,primecell |
| - description: The improved version of the block, found in the |
| ARM Versatile and later reference designs. Further revisions |
| exist but get detected at runtime by reading some magic numbers |
| in the PrimeCell ID registers. |
| items: |
| - const: arm,pl181 |
| - const: arm,primecell |
| - description: Wildcard entry that will let the operating system |
| inspect the PrimeCell ID registers to determine which hardware |
| variant of PL180 or PL181 this is. |
| items: |
| - const: arm,pl18x |
| - const: arm,primecell |
| - description: Entries for STMicroelectronics variant of PL18x. |
| items: |
| - enum: |
| - st,stm32-sdmmc2 |
| - st,stm32mp25-sdmmc2 |
| - const: arm,pl18x |
| - const: arm,primecell |
| |
| clocks: |
| description: One or two clocks, the "apb_pclk" and the "MCLK" |
| which is the core block clock. The names are not compulsory. |
| minItems: 1 |
| maxItems: 2 |
| |
| dmas: |
| maxItems: 2 |
| |
| dma-names: |
| oneOf: |
| - items: |
| - const: tx |
| - const: rx |
| - items: |
| - const: rx |
| - const: tx |
| |
| access-controllers: |
| minItems: 1 |
| maxItems: 2 |
| |
| power-domains: true |
| |
| resets: |
| maxItems: 1 |
| |
| reg: |
| description: the MMIO memory window must be exactly 4KB (0x1000) and the |
| layout should provide the PrimeCell ID registers so that the device can |
| be discovered. On ST Micro variants, a second register window may be |
| defined if a delay block is present and used for tuning. |
| |
| interrupts: |
| description: The first interrupt is the command interrupt and corresponds |
| to the event at the end of a command. The second interrupt is the |
| PIO (polled I/O) interrupt and occurs when the FIFO needs to be |
| emptied as part of a bulk read from the card. Some variants have these |
| two interrupts wired into the same line (logic OR) and in that case |
| only one interrupt may be provided. The interrupt-names property is |
| not used due to inconsistency of existing DTs regarding its content. |
| deprecated: false |
| minItems: 1 |
| maxItems: 2 |
| |
| st,sig-dir-dat0: |
| $ref: /schemas/types.yaml#/definitions/flag |
| description: ST Micro-specific property, bus signal direction pins used for |
| DAT[0]. |
| |
| st,sig-dir-dat2: |
| $ref: /schemas/types.yaml#/definitions/flag |
| description: ST Micro-specific property, bus signal direction pins used for |
| DAT[2]. |
| |
| st,sig-dir-dat31: |
| $ref: /schemas/types.yaml#/definitions/flag |
| description: ST Micro-specific property, bus signal direction pins used for |
| DAT[3] and DAT[1]. |
| |
| st,sig-dir-dat74: |
| $ref: /schemas/types.yaml#/definitions/flag |
| description: ST Micro-specific property, bus signal direction pins used for |
| DAT[7] and DAT[4]. |
| |
| st,sig-dir-cmd: |
| $ref: /schemas/types.yaml#/definitions/flag |
| description: ST Micro-specific property, CMD signal direction used for |
| pin CMD. |
| |
| st,sig-pin-fbclk: |
| $ref: /schemas/types.yaml#/definitions/flag |
| description: ST Micro-specific property, feedback clock FBCLK signal pin |
| in use. |
| |
| st,sig-dir: |
| $ref: /schemas/types.yaml#/definitions/flag |
| description: ST Micro-specific property, signal direction polarity used for |
| pins CMD, DAT[0], DAT[1], DAT[2] and DAT[3]. |
| |
| st,neg-edge: |
| $ref: /schemas/types.yaml#/definitions/flag |
| description: ST Micro-specific property, data and command phase relation, |
| generated on the sd clock falling edge. |
| |
| st,use-ckin: |
| $ref: /schemas/types.yaml#/definitions/flag |
| description: ST Micro-specific property, use CKIN pin from an external |
| driver to sample the receive data (for example with a voltage switch |
| transceiver). |
| |
| st,cmd-gpios: |
| maxItems: 1 |
| description: |
| The GPIO matching the CMD pin. |
| |
| st,ck-gpios: |
| maxItems: 1 |
| description: |
| The GPIO matching the CK pin. |
| |
| st,ckin-gpios: |
| maxItems: 1 |
| description: |
| The GPIO matching the CKIN pin. |
| |
| dependencies: |
| st,cmd-gpios: [ "st,use-ckin" ] |
| st,ck-gpios: [ "st,use-ckin" ] |
| st,ckin-gpios: [ "st,use-ckin" ] |
| |
| unevaluatedProperties: false |
| |
| required: |
| - compatible |
| - reg |
| - interrupts |
| |
| examples: |
| - | |
| #include <dt-bindings/interrupt-controller/irq.h> |
| #include <dt-bindings/gpio/gpio.h> |
| |
| mmc@5000 { |
| compatible = "arm,pl180", "arm,primecell"; |
| reg = <0x5000 0x1000>; |
| interrupts-extended = <&vic 22 &sic 1>; |
| clocks = <&xtal24mhz>, <&pclk>; |
| clock-names = "mclk", "apb_pclk"; |
| }; |
| |
| - | |
| #include <dt-bindings/interrupt-controller/irq.h> |
| |
| mmc@80126000 { |
| compatible = "arm,pl18x", "arm,primecell"; |
| reg = <0x80126000 0x1000>; |
| interrupts = <0 60 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&dma 29 0 0x2>, <&dma 29 0 0x0>; |
| dma-names = "rx", "tx"; |
| clocks = <&prcc_kclk 1 5>, <&prcc_pclk 1 5>; |
| clock-names = "sdi", "apb_pclk"; |
| max-frequency = <100000000>; |
| bus-width = <4>; |
| cap-sd-highspeed; |
| cap-mmc-highspeed; |
| cd-gpios = <&gpio2 31 0x4>; |
| st,sig-dir-dat0; |
| st,sig-dir-dat2; |
| st,sig-dir-cmd; |
| st,sig-pin-fbclk; |
| vmmc-supply = <&ab8500_ldo_aux3_reg>; |
| vqmmc-supply = <&vmmci>; |
| }; |
| |
| - | |
| mmc@101f6000 { |
| compatible = "arm,pl18x", "arm,primecell"; |
| reg = <0x101f6000 0x1000>; |
| clocks = <&sdiclk>, <&pclksdi>; |
| clock-names = "mclk", "apb_pclk"; |
| interrupts = <22>; |
| max-frequency = <400000>; |
| bus-width = <4>; |
| cap-mmc-highspeed; |
| cap-sd-highspeed; |
| full-pwr-cycle; |
| st,sig-dir-dat0; |
| st,sig-dir-dat2; |
| st,sig-dir-dat31; |
| st,sig-dir-cmd; |
| st,sig-pin-fbclk; |
| vmmc-supply = <&vmmc_regulator>; |
| }; |
| |
| - | |
| mmc@52007000 { |
| compatible = "arm,pl18x", "arm,primecell"; |
| arm,primecell-periphid = <0x10153180>; |
| reg = <0x52007000 0x1000>; |
| interrupts = <49>; |
| clocks = <&rcc 0>; |
| clock-names = "apb_pclk"; |
| resets = <&rcc 1>; |
| cap-sd-highspeed; |
| cap-mmc-highspeed; |
| max-frequency = <120000000>; |
| }; |
