Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml

# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Cadence Torrent SD0801 PHY

description:
  This binding describes the Cadence SD0801 PHY (also known as Torrent PHY)
  hardware included with the Cadence MHDP DisplayPort controller. Torrent
  PHY also supports multilink multiprotocol combinations including protocols
  such as PCIe, USB, SGMII, QSGMII etc.

maintainers:
  - Swapnil Jakhade <sjakhade@cadence.com>
  - Yuti Amonkar <yamonkar@cadence.com>

properties:
  compatible:
    enum:
      - cdns,torrent-phy
      - ti,j7200-serdes-10g
      - ti,j721e-serdes-10g

  '#address-cells':
    const: 1

  '#size-cells':
    const: 0

  '#clock-cells':
    const: 1

  clocks:
    minItems: 1
    maxItems: 2
    description:
      PHY input reference clocks - refclk (for PLL0) & pll1_refclk (for PLL1).
      pll1_refclk is optional and used for multi-protocol configurations requiring
      separate reference clock for each protocol.
      Same refclk is used for both PLL0 and PLL1 if no separate pll1_refclk is used.
      Optional parent clock (phy_en_refclk) to enable a reference clock output feature
      on some platforms to output either derived or received reference clock.

  clock-names:
    minItems: 1
    items:
      - const: refclk
      - enum: [ pll1_refclk, phy_en_refclk ]

  reg:
    minItems: 1
    items:
      - description: Offset of the Torrent PHY configuration registers.
      - description: Offset of the DPTX PHY configuration registers.

  reg-names:
    minItems: 1
    items:
      - const: torrent_phy
      - const: dptx_phy

  resets:
    minItems: 1
    items:
      - description: Torrent PHY reset.
      - description: Torrent APB reset. This is optional.

  reset-names:
    minItems: 1
    items:
      - const: torrent_reset
      - const: torrent_apb

patternProperties:
  '^phy@[0-3]$':
    type: object
    description:
      Each group of PHY lanes with a single master lane should be represented as a sub-node.
    properties:
      reg:
        description:
          The master lane number. This is the lowest numbered lane in the lane group.
        minimum: 0
        maximum: 3

      resets:
        minItems: 1
        maxItems: 4
        description:
          Contains list of resets, one per lane, to get all the link lanes out of reset.

      "#phy-cells":
        const: 0

      cdns,phy-type:
        description:
          Specifies the type of PHY for which the group of PHY lanes is used.
          Refer include/dt-bindings/phy/phy.h. Constants from the header should be used.
        $ref: /schemas/types.yaml#/definitions/uint32
        minimum: 1
        maximum: 9

      cdns,num-lanes:
        description:
          Number of lanes.
        $ref: /schemas/types.yaml#/definitions/uint32
        enum: [1, 2, 3, 4]
        default: 4

      cdns,ssc-mode:
        description:
          Specifies the Spread Spectrum Clocking mode used. It can be NO_SSC,
          EXTERNAL_SSC or INTERNAL_SSC.
          Refer include/dt-bindings/phy/phy-cadence.h for the constants to be used.
        $ref: /schemas/types.yaml#/definitions/uint32
        enum: [0, 1, 2]
        default: 0

      cdns,max-bit-rate:
        description:
          Maximum DisplayPort link bit rate to use, in Mbps
        $ref: /schemas/types.yaml#/definitions/uint32
        enum: [2160, 2430, 2700, 3240, 4320, 5400, 8100]
        default: 8100

    required:
      - reg
      - resets
      - "#phy-cells"
      - cdns,phy-type
      - cdns,num-lanes

    additionalProperties: false

required:
  - compatible
  - "#address-cells"
  - "#size-cells"
  - clocks
  - clock-names
  - reg
  - reg-names
  - resets
  - reset-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/phy/phy.h>

    bus {
        #address-cells = <2>;
        #size-cells = <2>;

        torrent-phy@f0fb500000 {
            compatible = "cdns,torrent-phy";
            reg = <0xf0 0xfb500000 0x0 0x00100000>,
                  <0xf0 0xfb030a00 0x0 0x00000040>;
            reg-names = "torrent_phy", "dptx_phy";
            resets = <&phyrst 0>;
            reset-names = "torrent_reset";
            clocks = <&ref_clk>;
            clock-names = "refclk";
            #address-cells = <1>;
            #size-cells = <0>;
            phy@0 {
                reg = <0>;
                resets = <&phyrst 1>, <&phyrst 2>,
                         <&phyrst 3>, <&phyrst 4>;
                #phy-cells = <0>;
                cdns,phy-type = <PHY_TYPE_DP>;
                cdns,num-lanes = <4>;
                cdns,max-bit-rate = <8100>;
            };
        };
    };
  - |
    #include <dt-bindings/phy/phy.h>
    #include <dt-bindings/phy/phy-cadence.h>

    bus {
        #address-cells = <2>;
        #size-cells = <2>;

        torrent-phy@f0fb500000 {
            compatible = "cdns,torrent-phy";
            reg = <0xf0 0xfb500000 0x0 0x00100000>;
            reg-names = "torrent_phy";
            resets = <&phyrst 0>, <&phyrst 1>;
            reset-names = "torrent_reset", "torrent_apb";
            clocks = <&ref_clk>;
            clock-names = "refclk";
            #address-cells = <1>;
            #size-cells = <0>;
            phy@0 {
                reg = <0>;
                resets = <&phyrst 2>, <&phyrst 3>;
                #phy-cells = <0>;
                cdns,phy-type = <PHY_TYPE_PCIE>;
                cdns,num-lanes = <2>;
                cdns,ssc-mode = <CDNS_SERDES_NO_SSC>;
            };

            phy@2 {
                reg = <2>;
                resets = <&phyrst 4>;
                #phy-cells = <0>;
                cdns,phy-type = <PHY_TYPE_SGMII>;
                cdns,num-lanes = <1>;
                cdns,ssc-mode = <CDNS_SERDES_NO_SSC>;
            };
        };
    };
...