| // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| /* |
| * Device Tree Include file for Marvell Armada 37xx family of SoCs. |
| * |
| * Copyright (C) 2016 Marvell |
| * |
| * Gregory CLEMENT <gregory.clement@free-electrons.com> |
| * |
| */ |
| |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| |
| / { |
| model = "Marvell Armada 37xx SoC"; |
| compatible = "marvell,armada3700"; |
| interrupt-parent = <&gic>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| aliases { |
| serial0 = &uart0; |
| serial1 = &uart1; |
| }; |
| |
| reserved-memory { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| /* |
| * The PSCI firmware region depicted below is the default one |
| * and should be updated by the bootloader. |
| */ |
| psci-area@4000000 { |
| reg = <0 0x4000000 0 0x200000>; |
| no-map; |
| }; |
| |
| tee@4400000 { |
| reg = <0 0x4400000 0 0x1000000>; |
| no-map; |
| }; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| cpu0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| reg = <0>; |
| clocks = <&nb_periph_clk 16>; |
| enable-method = "psci"; |
| }; |
| }; |
| |
| psci { |
| compatible = "arm,psci-0.2"; |
| method = "smc"; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| pmu { |
| compatible = "arm,cortex-a53-pmu"; |
| interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| soc { |
| compatible = "simple-bus"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| internal-regs@d0000000 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "simple-bus"; |
| /* 32M internal register @ 0xd000_0000 */ |
| ranges = <0x0 0x0 0xd0000000 0x2000000>; |
| |
| wdt: watchdog@8300 { |
| compatible = "marvell,armada-3700-wdt"; |
| reg = <0x8300 0x40>; |
| marvell,system-controller = <&cpu_misc>; |
| clocks = <&xtalclk>; |
| }; |
| |
| cpu_misc: system-controller@d000 { |
| compatible = "marvell,armada-3700-cpu-misc", |
| "syscon"; |
| reg = <0xd000 0x1000>; |
| }; |
| |
| spi0: spi@10600 { |
| compatible = "marvell,armada-3700-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x10600 0xA00>; |
| clocks = <&nb_periph_clk 7>; |
| interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; |
| num-cs = <4>; |
| status = "disabled"; |
| }; |
| |
| i2c0: i2c@11000 { |
| compatible = "marvell,armada-3700-i2c"; |
| reg = <0x11000 0x24>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&nb_periph_clk 10>; |
| interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; |
| mrvl,i2c-fast-mode; |
| status = "disabled"; |
| }; |
| |
| i2c1: i2c@11080 { |
| compatible = "marvell,armada-3700-i2c"; |
| reg = <0x11080 0x24>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&nb_periph_clk 9>; |
| interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; |
| mrvl,i2c-fast-mode; |
| status = "disabled"; |
| }; |
| |
| avs: avs@11500 { |
| compatible = "marvell,armada-3700-avs", |
| "syscon"; |
| reg = <0x11500 0x40>; |
| }; |
| |
| uartclk: clock-controller@12010 { |
| compatible = "marvell,armada-3700-uart-clock"; |
| reg = <0x12010 0x4>, <0x12210 0x4>; |
| clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, |
| <&tbg 3>, <&xtalclk>; |
| clock-names = "TBG-A-P", "TBG-B-P", "TBG-A-S", |
| "TBG-B-S", "xtal"; |
| #clock-cells = <1>; |
| }; |
| |
| uart0: serial@12000 { |
| compatible = "marvell,armada-3700-uart"; |
| reg = <0x12000 0x18>; |
| clocks = <&uartclk 0>; |
| interrupts = |
| <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "uart-sum", "uart-tx", "uart-rx"; |
| status = "disabled"; |
| }; |
| |
| uart1: serial@12200 { |
| compatible = "marvell,armada-3700-uart-ext"; |
| reg = <0x12200 0x30>; |
| clocks = <&uartclk 1>; |
| interrupts = |
| <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>; |
| interrupt-names = "uart-tx", "uart-rx"; |
| status = "disabled"; |
| }; |
| |
| nb_periph_clk: nb-periph-clk@13000 { |
| compatible = "marvell,armada-3700-periph-clock-nb", |
| "syscon"; |
| reg = <0x13000 0x100>; |
| clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, |
| <&tbg 3>, <&xtalclk>; |
| #clock-cells = <1>; |
| }; |
| |
| sb_periph_clk: sb-periph-clk@18000 { |
| compatible = "marvell,armada-3700-periph-clock-sb"; |
| reg = <0x18000 0x100>; |
| clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, |
| <&tbg 3>, <&xtalclk>; |
| #clock-cells = <1>; |
| }; |
| |
| tbg: tbg@13200 { |
| compatible = "marvell,armada-3700-tbg-clock"; |
| reg = <0x13200 0x100>; |
| clocks = <&xtalclk>; |
| #clock-cells = <1>; |
| }; |
| |
| pinctrl_nb: pinctrl@13800 { |
| compatible = "marvell,armada3710-nb-pinctrl", |
| "syscon", "simple-mfd"; |
| reg = <0x13800 0x100>, <0x13C00 0x20>; |
| /* MPP1[19:0] */ |
| gpionb: gpio { |
| #gpio-cells = <2>; |
| gpio-ranges = <&pinctrl_nb 0 0 36>; |
| gpio-controller; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| interrupts = |
| <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| xtalclk: xtal-clk { |
| compatible = "marvell,armada-3700-xtal-clock"; |
| clock-output-names = "xtal"; |
| #clock-cells = <0>; |
| }; |
| |
| spi_quad_pins: spi-quad-pins { |
| groups = "spi_quad"; |
| function = "spi"; |
| }; |
| |
| spi_cs1_pins: spi-cs1-pins { |
| groups = "spi_cs1"; |
| function = "spi"; |
| }; |
| |
| i2c1_pins: i2c1-pins { |
| groups = "i2c1"; |
| function = "i2c"; |
| }; |
| |
| i2c2_pins: i2c2-pins { |
| groups = "i2c2"; |
| function = "i2c"; |
| }; |
| |
| uart1_pins: uart1-pins { |
| groups = "uart1"; |
| function = "uart"; |
| }; |
| |
| uart2_pins: uart2-pins { |
| groups = "uart2"; |
| function = "uart"; |
| }; |
| |
| mmc_pins: mmc-pins { |
| groups = "emmc_nb"; |
| function = "emmc"; |
| }; |
| }; |
| |
| nb_pm: syscon@14000 { |
| compatible = "marvell,armada-3700-nb-pm", |
| "syscon"; |
| reg = <0x14000 0x60>; |
| }; |
| |
| comphy: phy@18300 { |
| compatible = "marvell,comphy-a3700"; |
| reg = <0x18300 0x300>, |
| <0x1F000 0x400>, |
| <0x5C000 0x400>, |
| <0xe0178 0x8>; |
| reg-names = "comphy", |
| "lane1_pcie_gbe", |
| "lane0_usb3_gbe", |
| "lane2_sata_usb3"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&xtalclk>; |
| clock-names = "xtal"; |
| |
| comphy0: phy@0 { |
| reg = <0>; |
| #phy-cells = <1>; |
| }; |
| |
| comphy1: phy@1 { |
| reg = <1>; |
| #phy-cells = <1>; |
| }; |
| |
| comphy2: phy@2 { |
| reg = <2>; |
| #phy-cells = <1>; |
| }; |
| }; |
| |
| pinctrl_sb: pinctrl@18800 { |
| compatible = "marvell,armada3710-sb-pinctrl", |
| "syscon", "simple-mfd"; |
| reg = <0x18800 0x100>, <0x18C00 0x20>; |
| /* MPP2[23:0] */ |
| gpiosb: gpio { |
| #gpio-cells = <2>; |
| gpio-ranges = <&pinctrl_sb 0 0 30>; |
| gpio-controller; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| interrupts = |
| <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| rgmii_pins: mii-pins { |
| groups = "rgmii"; |
| function = "mii"; |
| }; |
| |
| smi_pins: smi-pins { |
| groups = "smi"; |
| function = "smi"; |
| }; |
| |
| sdio_pins: sdio-pins { |
| groups = "sdio_sb"; |
| function = "sdio"; |
| }; |
| |
| pcie_reset_pins: pcie-reset-pins { |
| groups = "pcie1"; /* this actually controls "pcie1_reset" */ |
| function = "gpio"; |
| }; |
| |
| pcie_clkreq_pins: pcie-clkreq-pins { |
| groups = "pcie1_clkreq"; |
| function = "pcie"; |
| }; |
| }; |
| |
| eth0: ethernet@30000 { |
| compatible = "marvell,armada-3700-neta"; |
| reg = <0x30000 0x4000>; |
| interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&sb_periph_clk 8>; |
| status = "disabled"; |
| }; |
| |
| mdio: mdio@32004 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "marvell,orion-mdio"; |
| reg = <0x32004 0x4>; |
| }; |
| |
| eth1: ethernet@40000 { |
| compatible = "marvell,armada-3700-neta"; |
| reg = <0x40000 0x4000>; |
| interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&sb_periph_clk 7>; |
| status = "disabled"; |
| }; |
| |
| usb3: usb@58000 { |
| compatible = "marvell,armada3700-xhci", |
| "generic-xhci"; |
| reg = <0x58000 0x4000>; |
| marvell,usb-misc-reg = <&usb32_syscon>; |
| interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&sb_periph_clk 12>; |
| phys = <&comphy0 0>, <&usb2_utmi_otg_phy>; |
| phy-names = "usb3-phy", "usb2-utmi-otg-phy"; |
| status = "disabled"; |
| }; |
| |
| usb2_utmi_otg_phy: phy@5d000 { |
| compatible = "marvell,a3700-utmi-otg-phy"; |
| reg = <0x5d000 0x800>; |
| marvell,usb-misc-reg = <&usb32_syscon>; |
| #phy-cells = <0>; |
| }; |
| |
| usb32_syscon: system-controller@5d800 { |
| compatible = "marvell,armada-3700-usb2-host-device-misc", |
| "syscon"; |
| reg = <0x5d800 0x800>; |
| }; |
| |
| usb2: usb@5e000 { |
| compatible = "marvell,armada-3700-ehci"; |
| reg = <0x5e000 0x1000>; |
| marvell,usb-misc-reg = <&usb2_syscon>; |
| interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; |
| phys = <&usb2_utmi_host_phy>; |
| phy-names = "usb2-utmi-host-phy"; |
| status = "disabled"; |
| }; |
| |
| usb2_utmi_host_phy: phy@5f000 { |
| compatible = "marvell,a3700-utmi-host-phy"; |
| reg = <0x5f000 0x800>; |
| marvell,usb-misc-reg = <&usb2_syscon>; |
| #phy-cells = <0>; |
| }; |
| |
| usb2_syscon: system-controller@5f800 { |
| compatible = "marvell,armada-3700-usb2-host-misc", |
| "syscon"; |
| reg = <0x5f800 0x800>; |
| }; |
| |
| xor@60900 { |
| compatible = "marvell,armada-3700-xor"; |
| reg = <0x60900 0x100>, |
| <0x60b00 0x100>; |
| |
| xor10 { |
| interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| xor11 { |
| interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| }; |
| |
| crypto: crypto@90000 { |
| compatible = "inside-secure,safexcel-eip97ies"; |
| reg = <0x90000 0x20000>; |
| interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "ring0", "ring1", "ring2", |
| "ring3", "eip", "mem"; |
| clocks = <&nb_periph_clk 15>; |
| }; |
| |
| rwtm: mailbox@b0000 { |
| compatible = "marvell,armada-3700-rwtm-mailbox"; |
| reg = <0xb0000 0x100>; |
| interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; |
| #mbox-cells = <1>; |
| }; |
| |
| sdhci1: mmc@d0000 { |
| compatible = "marvell,armada-3700-sdhci", |
| "marvell,sdhci-xenon"; |
| reg = <0xd0000 0x300>, |
| <0x1e808 0x4>; |
| interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&nb_periph_clk 0>; |
| clock-names = "core"; |
| status = "disabled"; |
| }; |
| |
| sdhci0: mmc@d8000 { |
| compatible = "marvell,armada-3700-sdhci", |
| "marvell,sdhci-xenon"; |
| reg = <0xd8000 0x300>, |
| <0x17808 0x4>; |
| interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&nb_periph_clk 0>; |
| clock-names = "core"; |
| status = "disabled"; |
| }; |
| |
| sata: sata@e0000 { |
| compatible = "marvell,armada-3700-ahci"; |
| reg = <0xe0000 0x178>; |
| interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&nb_periph_clk 1>; |
| phys = <&comphy2 0>; |
| phy-names = "sata-phy"; |
| status = "disabled"; |
| }; |
| |
| gic: interrupt-controller@1d00000 { |
| compatible = "arm,gic-v3"; |
| #interrupt-cells = <3>; |
| interrupt-controller; |
| reg = <0x1d00000 0x10000>, /* GICD */ |
| <0x1d40000 0x40000>, /* GICR */ |
| <0x1d80000 0x2000>, /* GICC */ |
| <0x1d90000 0x2000>, /* GICH */ |
| <0x1da0000 0x20000>; /* GICV */ |
| interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| }; |
| |
| pcie0: pcie@d0070000 { |
| compatible = "marvell,armada-3700-pcie"; |
| device_type = "pci"; |
| status = "disabled"; |
| reg = <0 0xd0070000 0 0x20000>; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| bus-range = <0x00 0xff>; |
| interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; |
| #interrupt-cells = <1>; |
| clocks = <&sb_periph_clk 13>; |
| msi-parent = <&pcie0>; |
| msi-controller; |
| /* |
| * The 128 MiB address range [0xe8000000-0xf0000000] is |
| * dedicated for PCIe and can be assigned to 8 windows |
| * with size a power of two. Use one 64 KiB window for |
| * IO at the end and the remaining seven windows |
| * (totaling 127 MiB) for MEM. |
| */ |
| ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x07f00000 /* Port 0 MEM */ |
| 0x81000000 0 0x00000000 0 0xefff0000 0 0x00010000>; /* Port 0 IO */ |
| interrupt-map-mask = <0 0 0 7>; |
| interrupt-map = <0 0 0 1 &pcie_intc 0>, |
| <0 0 0 2 &pcie_intc 1>, |
| <0 0 0 3 &pcie_intc 2>, |
| <0 0 0 4 &pcie_intc 3>; |
| max-link-speed = <2>; |
| phys = <&comphy1 0>; |
| pcie_intc: interrupt-controller { |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| }; |
| |
| firmware { |
| armada-3700-rwtm { |
| compatible = "marvell,armada-3700-rwtm-firmware"; |
| mboxes = <&rwtm 0>; |
| status = "okay"; |
| }; |
| }; |
| }; |
