| // SPDX-License-Identifier: GPL-2.0+ |
| /* |
| * Copyright (C) 2024 Josua Mayer <josua@solid-run.com> |
| * |
| * DTS for SolidRun CN9130 Clearfog Pro. |
| * |
| */ |
| |
| /dts-v1/; |
| |
| #include <dt-bindings/input/input.h> |
| #include <dt-bindings/leds/common.h> |
| |
| #include "cn9130.dtsi" |
| #include "cn9130-sr-som.dtsi" |
| #include "cn9130-cf.dtsi" |
| |
| / { |
| model = "SolidRun CN9130 Clearfog Pro"; |
| compatible = "solidrun,cn9130-clearfog-pro", |
| "solidrun,cn9130-sr-som", "marvell,cn9130"; |
| |
| gpio-keys { |
| compatible = "gpio-keys"; |
| pinctrl-0 = <&rear_button_pins>; |
| pinctrl-names = "default"; |
| |
| button-0 { |
| /* The rear SW3 button */ |
| label = "Rear Button"; |
| gpios = <&cp0_gpio2 0 GPIO_ACTIVE_LOW>; |
| linux,can-disable; |
| linux,code = <BTN_0>; |
| }; |
| }; |
| }; |
| |
| /* SRDS #3 - SGMII 1GE to L2 switch */ |
| &cp0_eth1 { |
| phys = <&cp0_comphy3 1>; |
| phy-mode = "sgmii"; |
| status = "okay"; |
| |
| fixed-link { |
| speed = <1000>; |
| full-duplex; |
| }; |
| }; |
| |
| &cp0_eth2_phy { |
| /* |
| * Configure LEDs default behaviour similar to switch ports: |
| * - LED[0]: link/activity: On/blink (green) |
| * - LED[1]: link is 100/1000Mbps: On (red) |
| * - LED[2]: high impedance (floating) |
| * |
| * Switch port defaults: |
| * - LED0: link/activity: On/blink (green) |
| * - LED1: link is 1000Mbps: On (red) |
| * |
| * Identical configuration is impossible with hardware offload. |
| */ |
| marvell,reg-init = <3 16 0xf000 0x0a61>; |
| |
| leds { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| led@0 { |
| reg = <0>; |
| color = <LED_COLOR_ID_GREEN>; |
| function = LED_FUNCTION_WAN; |
| label = "LED2"; |
| default-state = "keep"; |
| }; |
| |
| led@1 { |
| reg = <1>; |
| color = <LED_COLOR_ID_RED>; |
| function = LED_FUNCTION_WAN; |
| label = "LED1"; |
| default-state = "keep"; |
| }; |
| }; |
| }; |
| |
| &cp0_mdio { |
| ethernet-switch@4 { |
| compatible = "marvell,mv88e6085"; |
| reg = <4>; |
| pinctrl-0 = <&dsa_clk_pins &dsa_pins>; |
| pinctrl-names = "default"; |
| reset-gpios = <&cp0_gpio1 27 GPIO_ACTIVE_LOW>; |
| interrupt-parent = <&cp0_gpio1>; |
| interrupts = <29 IRQ_TYPE_EDGE_FALLING>; |
| |
| ethernet-ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| ethernet-port@0 { |
| reg = <0>; |
| label = "lan5"; |
| phy = <&switch0phy0>; |
| |
| leds { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| led@0 { |
| reg = <0>; |
| color = <LED_COLOR_ID_GREEN>; |
| function = LED_FUNCTION_LAN; |
| label = "LED12"; |
| default-state = "keep"; |
| }; |
| |
| led@1 { |
| reg = <1>; |
| color = <LED_COLOR_ID_RED>; |
| function = LED_FUNCTION_LAN; |
| label = "LED11"; |
| default-state = "keep"; |
| }; |
| }; |
| }; |
| |
| ethernet-port@1 { |
| reg = <1>; |
| label = "lan4"; |
| phy = <&switch0phy1>; |
| |
| leds { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| led@0 { |
| reg = <0>; |
| color = <LED_COLOR_ID_GREEN>; |
| function = LED_FUNCTION_LAN; |
| label = "LED10"; |
| default-state = "keep"; |
| }; |
| |
| led@1 { |
| reg = <1>; |
| color = <LED_COLOR_ID_RED>; |
| function = LED_FUNCTION_LAN; |
| label = "LED9"; |
| default-state = "keep"; |
| }; |
| }; |
| }; |
| |
| ethernet-port@2 { |
| reg = <2>; |
| label = "lan3"; |
| phy = <&switch0phy2>; |
| |
| leds { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| led@0 { |
| reg = <0>; |
| color = <LED_COLOR_ID_GREEN>; |
| function = LED_FUNCTION_LAN; |
| label = "LED8"; |
| default-state = "keep"; |
| }; |
| |
| led@1 { |
| reg = <1>; |
| color = <LED_COLOR_ID_RED>; |
| function = LED_FUNCTION_LAN; |
| label = "LED7"; |
| default-state = "keep"; |
| }; |
| }; |
| }; |
| |
| ethernet-port@3 { |
| reg = <3>; |
| label = "lan2"; |
| phy = <&switch0phy3>; |
| |
| leds { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| led@0 { |
| reg = <0>; |
| color = <LED_COLOR_ID_GREEN>; |
| function = LED_FUNCTION_LAN; |
| label = "LED6"; |
| default-state = "keep"; |
| }; |
| |
| led@1 { |
| reg = <1>; |
| color = <LED_COLOR_ID_RED>; |
| function = LED_FUNCTION_LAN; |
| label = "LED5"; |
| default-state = "keep"; |
| }; |
| }; |
| }; |
| |
| ethernet-port@4 { |
| reg = <4>; |
| label = "lan1"; |
| phy = <&switch0phy4>; |
| |
| leds { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| led@0 { |
| reg = <0>; |
| color = <LED_COLOR_ID_GREEN>; |
| function = LED_FUNCTION_LAN; |
| label = "LED4"; |
| default-state = "keep"; |
| }; |
| |
| led@1 { |
| reg = <1>; |
| color = <LED_COLOR_ID_RED>; |
| function = LED_FUNCTION_LAN; |
| label = "LED3"; |
| default-state = "keep"; |
| }; |
| }; |
| }; |
| |
| ethernet-port@5 { |
| reg = <5>; |
| label = "cpu"; |
| ethernet = <&cp0_eth1>; |
| phy-mode = "sgmii"; |
| |
| fixed-link { |
| speed = <1000>; |
| full-duplex; |
| }; |
| }; |
| |
| ethernet-port@6 { |
| reg = <6>; |
| label = "lan6"; |
| phy-mode = "rgmii"; |
| |
| /* |
| * Because of mdio address conflict the |
| * external phy is not readable. |
| * Force a fixed link instead. |
| */ |
| fixed-link { |
| speed = <1000>; |
| full-duplex; |
| }; |
| }; |
| }; |
| |
| mdio { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| switch0phy0: ethernet-phy@0 { |
| reg = <0x0>; |
| }; |
| |
| switch0phy1: ethernet-phy@1 { |
| reg = <0x1>; |
| /* |
| * Indirectly configure default behaviour |
| * for port lan6 leds behind external phy. |
| * Internal PHYs are not using page 3, |
| * therefore writing to it is safe. |
| */ |
| marvell,reg-init = <3 16 0xf000 0x0a61>; |
| }; |
| |
| switch0phy2: ethernet-phy@2 { |
| reg = <0x2>; |
| }; |
| |
| switch0phy3: ethernet-phy@3 { |
| reg = <0x3>; |
| }; |
| |
| switch0phy4: ethernet-phy@4 { |
| reg = <0x4>; |
| }; |
| }; |
| |
| /* |
| * There is an external phy on the switch mdio bus. |
| * Because its mdio address collides with internal phys, |
| * it is not readable. |
| * |
| * mdio-external { |
| * compatible = "marvell,mv88e6xxx-mdio-external"; |
| * #address-cells = <1>; |
| * #size-cells = <0>; |
| * |
| * ethernet-phy@1 { |
| * reg = <0x1>; |
| * }; |
| * }; |
| */ |
| }; |
| }; |
| |
| /* SRDS #4 - miniPCIe (CON2) */ |
| &cp0_pcie1 { |
| num-lanes = <1>; |
| phys = <&cp0_comphy4 1>; |
| /* dw-pcie inverts internally */ |
| reset-gpios = <&expander0 2 GPIO_ACTIVE_HIGH>; |
| status = "okay"; |
| }; |
| |
| &cp0_pinctrl { |
| dsa_clk_pins: cp0-dsa-clk-pins { |
| marvell,pins = "mpp40"; |
| marvell,function = "synce1"; |
| }; |
| |
| dsa_pins: cp0-dsa-pins { |
| marvell,pins = "mpp27", "mpp29"; |
| marvell,function = "gpio"; |
| }; |
| |
| rear_button_pins: cp0-rear-button-pins { |
| marvell,pins = "mpp32"; |
| marvell,function = "gpio"; |
| }; |
| |
| cp0_spi1_cs1_pins: cp0-spi1-cs1-pins { |
| marvell,pins = "mpp12"; |
| marvell,function = "spi1"; |
| }; |
| }; |
| |
| &cp0_spi1 { |
| /* add pin for chip-select 1 on mikrobus */ |
| pinctrl-0 = <&cp0_spi1_pins &cp0_spi1_cs1_pins>; |
| }; |
| |
| /* USB-2.0 Host on Type-A connector */ |
| &cp0_usb3_1 { |
| phys = <&cp0_utmi1>; |
| phy-names = "utmi"; |
| dr_mode = "host"; |
| status = "okay"; |
| }; |
| |
| &expander0 { |
| /* CON2 */ |
| pcie1-0-clkreq-hog { |
| gpio-hog; |
| gpios = <4 GPIO_ACTIVE_LOW>; |
| input; |
| line-name = "pcie1.0-clkreq"; |
| }; |
| |
| /* CON2 */ |
| pcie1-0-w-disable-hog { |
| gpio-hog; |
| gpios = <7 GPIO_ACTIVE_LOW>; |
| output-low; |
| line-name = "pcie1.0-w-disable"; |
| }; |
| }; |
