| /* SPDX-License-Identifier: GPL-2.0 */ | |
| /* | |
| * Copyright (c) 2023, Linaro Limited | |
| */ | |
| #ifndef QCOM_PHY_QMP_PCS_PCIE_V6_H_ | |
| #define QCOM_PHY_QMP_PCS_PCIE_V6_H_ | |
| /* Only for QMP V6 PHY - PCIE have different offsets than V5 */ | |
| #define QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG2 0x0c | |
| #define QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG4 0x14 | |
| #define QPHY_PCIE_V6_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20 | |
| #define QPHY_PCIE_V6_PCS_PCIE_OSC_DTCT_ACTIONS 0x94 | |
| #endif |