| [ |
| { |
| "ArchStdEvent": "SW_INCR" |
| }, |
| { |
| "ArchStdEvent": "INST_RETIRED" |
| }, |
| { |
| "ArchStdEvent": "EXC_RETURN" |
| }, |
| { |
| "ArchStdEvent": "CID_WRITE_RETIRED" |
| }, |
| { |
| "ArchStdEvent": "INST_SPEC" |
| }, |
| { |
| "ArchStdEvent": "TTBR_WRITE_RETIRED" |
| }, |
| { |
| "ArchStdEvent": "BR_RETIRED" |
| }, |
| { |
| "ArchStdEvent": "BR_MIS_PRED_RETIRED" |
| }, |
| { |
| "ArchStdEvent": "OP_RETIRED" |
| }, |
| { |
| "ArchStdEvent": "OP_SPEC" |
| }, |
| { |
| "ArchStdEvent": "LDREX_SPEC" |
| }, |
| { |
| "ArchStdEvent": "STREX_PASS_SPEC" |
| }, |
| { |
| "ArchStdEvent": "STREX_FAIL_SPEC" |
| }, |
| { |
| "ArchStdEvent": "STREX_SPEC" |
| }, |
| { |
| "ArchStdEvent": "LD_SPEC" |
| }, |
| { |
| "ArchStdEvent": "ST_SPEC" |
| }, |
| { |
| "ArchStdEvent": "DP_SPEC" |
| }, |
| { |
| "ArchStdEvent": "ASE_SPEC" |
| }, |
| { |
| "ArchStdEvent": "VFP_SPEC" |
| }, |
| { |
| "ArchStdEvent": "PC_WRITE_SPEC" |
| }, |
| { |
| "ArchStdEvent": "CRYPTO_SPEC" |
| }, |
| { |
| "ArchStdEvent": "BR_IMMED_SPEC" |
| }, |
| { |
| "ArchStdEvent": "BR_RETURN_SPEC" |
| }, |
| { |
| "ArchStdEvent": "BR_INDIRECT_SPEC" |
| }, |
| { |
| "ArchStdEvent": "ISB_SPEC" |
| }, |
| { |
| "ArchStdEvent": "DSB_SPEC" |
| }, |
| { |
| "ArchStdEvent": "DMB_SPEC" |
| }, |
| { |
| "ArchStdEvent": "RC_LD_SPEC" |
| }, |
| { |
| "ArchStdEvent": "RC_ST_SPEC" |
| }, |
| { |
| "ArchStdEvent": "ASE_INST_SPEC" |
| }, |
| { |
| "ArchStdEvent": "SVE_INST_SPEC" |
| }, |
| { |
| "ArchStdEvent": "FP_HP_SPEC" |
| }, |
| { |
| "ArchStdEvent": "FP_SP_SPEC" |
| }, |
| { |
| "ArchStdEvent": "FP_DP_SPEC" |
| }, |
| { |
| "ArchStdEvent": "SVE_PRED_SPEC" |
| }, |
| { |
| "ArchStdEvent": "SVE_PRED_EMPTY_SPEC" |
| }, |
| { |
| "ArchStdEvent": "SVE_PRED_FULL_SPEC" |
| }, |
| { |
| "ArchStdEvent": "SVE_PRED_PARTIAL_SPEC" |
| }, |
| { |
| "ArchStdEvent": "SVE_PRED_NOT_FULL_SPEC" |
| }, |
| { |
| "ArchStdEvent": "SVE_LDFF_SPEC" |
| }, |
| { |
| "ArchStdEvent": "SVE_LDFF_FAULT_SPEC" |
| }, |
| { |
| "ArchStdEvent": "FP_SCALE_OPS_SPEC" |
| }, |
| { |
| "ArchStdEvent": "FP_FIXED_OPS_SPEC" |
| }, |
| { |
| "ArchStdEvent": "ASE_SVE_INT8_SPEC" |
| }, |
| { |
| "ArchStdEvent": "ASE_SVE_INT16_SPEC" |
| }, |
| { |
| "ArchStdEvent": "ASE_SVE_INT32_SPEC" |
| }, |
| { |
| "ArchStdEvent": "ASE_SVE_INT64_SPEC" |
| } |
| ] |
