| # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| %YAML 1.2 |
| --- |
| $id: http://devicetree.org/schemas/mtd/mediatek,nand-ecc-engine.yaml# |
| $schema: http://devicetree.org/meta-schemas/core.yaml# |
| |
| title: MediaTek(MTK) SoCs NAND ECC engine |
| |
| maintainers: |
| - Xiangsheng Hou <xiangsheng.hou@mediatek.com> |
| |
| description: | |
| MTK NAND ECC engine can cowork with MTK raw NAND and SPI NAND controller. |
| |
| properties: |
| compatible: |
| enum: |
| - mediatek,mt2701-ecc |
| - mediatek,mt2712-ecc |
| - mediatek,mt7622-ecc |
| - mediatek,mt7986-ecc |
| |
| reg: |
| items: |
| - description: Base physical address and size of ECC. |
| |
| interrupts: |
| items: |
| - description: ECC interrupt |
| |
| clocks: |
| maxItems: 1 |
| |
| clock-names: |
| const: nfiecc_clk |
| |
| required: |
| - compatible |
| - reg |
| - interrupts |
| - clocks |
| - clock-names |
| |
| additionalProperties: false |
| |
| examples: |
| - | |
| #include <dt-bindings/clock/mt2701-clk.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/interrupt-controller/irq.h> |
| |
| soc { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| bch: ecc@1100e000 { |
| compatible = "mediatek,mt2701-ecc"; |
| reg = <0 0x1100e000 0 0x1000>; |
| interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&pericfg CLK_PERI_NFI_ECC>; |
| clock-names = "nfiecc_clk"; |
| }; |
| }; |
