| // SPDX-License-Identifier: GPL-2.0-only OR MIT |
| /* |
| * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ |
| * |
| * Design Files: https://www.ti.com/lit/zip/SPRR466 |
| * TRM: https://www.ti.com/lit/zip/spruj52 |
| */ |
| |
| /dts-v1/; |
| |
| #include <dt-bindings/net/ti-dp83867.h> |
| #include <dt-bindings/gpio/gpio.h> |
| #include "k3-j784s4.dtsi" |
| |
| / { |
| compatible = "ti,am69-sk", "ti,j784s4"; |
| model = "Texas Instruments AM69 SK"; |
| |
| chosen { |
| stdout-path = "serial2:115200n8"; |
| }; |
| |
| aliases { |
| serial0 = &wkup_uart0; |
| serial1 = &mcu_uart0; |
| serial2 = &main_uart8; |
| mmc0 = &main_sdhci0; |
| mmc1 = &main_sdhci1; |
| i2c0 = &wkup_i2c0; |
| i2c3 = &main_i2c0; |
| ethernet0 = &mcu_cpsw_port1; |
| }; |
| |
| memory@80000000 { |
| device_type = "memory"; |
| bootph-all; |
| /* 32G RAM */ |
| reg = <0x00 0x80000000 0x00 0x80000000>, |
| <0x08 0x80000000 0x07 0x80000000>; |
| }; |
| |
| reserved_memory: reserved-memory { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| secure_ddr: optee@9e800000 { |
| reg = <0x00 0x9e800000 0x00 0x01800000>; |
| no-map; |
| }; |
| |
| mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa0000000 0x00 0x100000>; |
| no-map; |
| }; |
| |
| mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa0100000 0x00 0xf00000>; |
| no-map; |
| }; |
| |
| mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa1000000 0x00 0x100000>; |
| no-map; |
| }; |
| |
| mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa1100000 0x00 0xf00000>; |
| no-map; |
| }; |
| |
| main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa2000000 0x00 0x100000>; |
| no-map; |
| }; |
| |
| main_r5fss0_core0_memory_region: r5f-memory@a2100000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa2100000 0x00 0xf00000>; |
| no-map; |
| }; |
| |
| main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa3000000 0x00 0x100000>; |
| no-map; |
| }; |
| |
| main_r5fss0_core1_memory_region: r5f-memory@a3100000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa3100000 0x00 0xf00000>; |
| no-map; |
| }; |
| |
| main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa4000000 0x00 0x100000>; |
| no-map; |
| }; |
| |
| main_r5fss1_core0_memory_region: r5f-memory@a4100000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa4100000 0x00 0xf00000>; |
| no-map; |
| }; |
| |
| main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa5000000 0x00 0x100000>; |
| no-map; |
| }; |
| |
| main_r5fss1_core1_memory_region: r5f-memory@a5100000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa5100000 0x00 0xf00000>; |
| no-map; |
| }; |
| |
| main_r5fss2_core0_dma_memory_region: r5f-dma-memory@a6000000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa6000000 0x00 0x100000>; |
| no-map; |
| }; |
| |
| main_r5fss2_core0_memory_region: r5f-memory@a6100000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa6100000 0x00 0xf00000>; |
| no-map; |
| }; |
| |
| main_r5fss2_core1_dma_memory_region: r5f-dma-memory@a7000000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa7000000 0x00 0x100000>; |
| no-map; |
| }; |
| |
| main_r5fss2_core1_memory_region: r5f-memory@a7100000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa7100000 0x00 0xf00000>; |
| no-map; |
| }; |
| |
| c71_0_dma_memory_region: c71-dma-memory@a8000000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa8000000 0x00 0x100000>; |
| no-map; |
| }; |
| |
| c71_0_memory_region: c71-memory@a8100000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa8100000 0x00 0xf00000>; |
| no-map; |
| }; |
| |
| c71_1_dma_memory_region: c71-dma-memory@a9000000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa9000000 0x00 0x100000>; |
| no-map; |
| }; |
| |
| c71_1_memory_region: c71-memory@a9100000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa9100000 0x00 0xf00000>; |
| no-map; |
| }; |
| |
| c71_2_dma_memory_region: c71-dma-memory@aa000000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xaa000000 0x00 0x100000>; |
| no-map; |
| }; |
| |
| c71_2_memory_region: c71-memory@aa100000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xaa100000 0x00 0xf00000>; |
| no-map; |
| }; |
| |
| c71_3_dma_memory_region: c71-dma-memory@ab000000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xab000000 0x00 0x100000>; |
| no-map; |
| }; |
| |
| c71_3_memory_region: c71-memory@ab100000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xab100000 0x00 0xf00000>; |
| no-map; |
| }; |
| }; |
| |
| vusb_main: regulator-vusb-main5v0 { |
| /* USB MAIN INPUT 5V DC */ |
| compatible = "regulator-fixed"; |
| regulator-name = "vusb-main5v0"; |
| regulator-min-microvolt = <5000000>; |
| regulator-max-microvolt = <5000000>; |
| regulator-always-on; |
| regulator-boot-on; |
| }; |
| |
| vsys_5v0: regulator-vsys5v0 { |
| /* Output of LM61460 */ |
| compatible = "regulator-fixed"; |
| regulator-name = "vsys_5v0"; |
| regulator-min-microvolt = <5000000>; |
| regulator-max-microvolt = <5000000>; |
| vin-supply = <&vusb_main>; |
| regulator-always-on; |
| regulator-boot-on; |
| }; |
| |
| vsys_3v3: regulator-vsys3v3 { |
| /* Output of LM5143 */ |
| compatible = "regulator-fixed"; |
| regulator-name = "vsys_3v3"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| vin-supply = <&vusb_main>; |
| regulator-always-on; |
| regulator-boot-on; |
| }; |
| |
| vdd_mmc1: regulator-sd { |
| /* Output of TPS22918 */ |
| compatible = "regulator-fixed"; |
| regulator-name = "vdd_mmc1"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-boot-on; |
| enable-active-high; |
| vin-supply = <&vsys_3v3>; |
| gpio = <&exp1 2 GPIO_ACTIVE_HIGH>; |
| }; |
| |
| vdd_sd_dv: regulator-tlv71033 { |
| /* Output of TLV71033 */ |
| compatible = "regulator-gpio"; |
| regulator-name = "tlv71033"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&vdd_sd_dv_pins_default>; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-boot-on; |
| vin-supply = <&vsys_5v0>; |
| gpios = <&main_gpio0 49 GPIO_ACTIVE_HIGH>; |
| states = <1800000 0x0>, |
| <3300000 0x1>; |
| }; |
| |
| dp0_pwr_3v3: regulator-dp0-pwr { |
| compatible = "regulator-fixed"; |
| regulator-name = "dp0-pwr"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&dp_pwr_en_pins_default>; |
| gpio = <&main_gpio0 4 0>; /* DP0_3V3 _EN */ |
| enable-active-high; |
| }; |
| |
| dp0: connector-dp0 { |
| compatible = "dp-connector"; |
| label = "DP0"; |
| type = "full-size"; |
| dp-pwr-supply = <&dp0_pwr_3v3>; |
| |
| port { |
| dp0_connector_in: endpoint { |
| remote-endpoint = <&dp0_out>; |
| }; |
| }; |
| }; |
| |
| connector-hdmi { |
| compatible = "hdmi-connector"; |
| label = "hdmi"; |
| type = "a"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&hdmi_hpd_pins_default>; |
| ddc-i2c-bus = <&mcu_i2c1>; |
| hpd-gpios = <&main_gpio0 0 GPIO_ACTIVE_HIGH>; /* HDMI_HPD */ |
| |
| port { |
| hdmi_connector_in: endpoint { |
| remote-endpoint = <&tfp410_out>; |
| }; |
| }; |
| }; |
| |
| bridge-dvi { |
| compatible = "ti,tfp410"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&hdmi_pdn_pins_default>; |
| powerdown-gpios = <&wkup_gpio0 14 GPIO_ACTIVE_LOW>; /* HDMI_PDn */ |
| ti,deskew = <0>; |
| |
| ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| reg = <0>; |
| |
| tfp410_in: endpoint { |
| remote-endpoint = <&dpi1_out0>; |
| pclk-sample = <1>; |
| }; |
| }; |
| |
| port@1 { |
| reg = <1>; |
| |
| tfp410_out: endpoint { |
| remote-endpoint = <&hdmi_connector_in>; |
| }; |
| }; |
| }; |
| }; |
| |
| csi_mux: mux-controller { |
| compatible = "gpio-mux"; |
| #mux-state-cells = <1>; |
| mux-gpios = <&exp2 1 GPIO_ACTIVE_HIGH>; |
| idle-state = <0>; |
| }; |
| |
| transceiver1: can-phy0 { |
| compatible = "ti,tcan1042"; |
| #phy-cells = <0>; |
| max-bitrate = <5000000>; |
| }; |
| |
| transceiver2: can-phy1 { |
| compatible = "ti,tcan1042"; |
| #phy-cells = <0>; |
| max-bitrate = <5000000>; |
| }; |
| |
| transceiver3: can-phy2 { |
| compatible = "ti,tcan1042"; |
| #phy-cells = <0>; |
| max-bitrate = <5000000>; |
| }; |
| |
| transceiver4: can-phy3 { |
| compatible = "ti,tcan1042"; |
| #phy-cells = <0>; |
| max-bitrate = <5000000>; |
| }; |
| |
| }; |
| |
| &main_pmx0 { |
| bootph-all; |
| main_uart8_pins_default: main-uart8-default-pins { |
| bootph-all; |
| pinctrl-single,pins = < |
| J784S4_IOPAD(0x0d0, PIN_INPUT, 11) /* (AP38) SPI0_CS1.UART8_RXD */ |
| J784S4_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AN38) SPI0_CLK.UART8_TXD */ |
| >; |
| }; |
| |
| main_i2c0_pins_default: main-i2c0-default-pins { |
| pinctrl-single,pins = < |
| J784S4_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AN36) I2C0_SCL */ |
| J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C0_SDA */ |
| >; |
| }; |
| |
| main_i2c1_pins_default: main-i2c1-default-pins { |
| pinctrl-single,pins = < |
| J784S4_IOPAD(0x0ac, PIN_INPUT_PULLUP, 13) /* (AE34) MCASP0_AXR15.I2C1_SCL */ |
| J784S4_IOPAD(0x0b0, PIN_INPUT_PULLUP, 13) /* (AL33) MCASP1_AXR3.I2C1_SDA */ |
| >; |
| }; |
| |
| main_mmc1_pins_default: main-mmc1-default-pins { |
| bootph-all; |
| pinctrl-single,pins = < |
| J784S4_IOPAD(0x104, PIN_INPUT, 0) /* (AB38) MMC1_CLK */ |
| J784S4_IOPAD(0x108, PIN_INPUT, 0) /* (AB36) MMC1_CMD */ |
| J784S4_IOPAD(0x100, PIN_INPUT, 0) /* (No Pin) MMC1_CLKLB */ |
| J784S4_IOPAD(0x0fc, PIN_INPUT, 0) /* (AA33) MMC1_DAT0 */ |
| J784S4_IOPAD(0x0f8, PIN_INPUT, 0) /* (AB34) MMC1_DAT1 */ |
| J784S4_IOPAD(0x0f4, PIN_INPUT, 0) /* (AA32) MMC1_DAT2 */ |
| J784S4_IOPAD(0x0f0, PIN_INPUT, 0) /* (AC38) MMC1_DAT3 */ |
| J784S4_IOPAD(0x0e8, PIN_INPUT, 8) /* (AR38) TIMER_IO0.MMC1_SDCD */ |
| >; |
| }; |
| |
| vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { |
| pinctrl-single,pins = < |
| J784S4_IOPAD(0x0C4, PIN_INPUT, 7) /* (AD36) ECAP0_IN_APWM_OUT.GPIO0_49 */ |
| >; |
| }; |
| |
| rpi_header_gpio0_pins_default: rpi-header-gpio0-default-pins { |
| pinctrl-single,pins = < |
| J784S4_IOPAD(0x0BC, PIN_INPUT, 7) /* (AD33) MCASP1_AFSX.GPIO0_47 */ |
| J784S4_IOPAD(0x06C, PIN_INPUT, 7) /* (AJ37) MCASP4_AFSX.GPIO0_27 */ |
| J784S4_IOPAD(0x0B4, PIN_INPUT, 7) /* (AL34) MCASP1_AXR4.GPIO0_45 */ |
| J784S4_IOPAD(0x0C0, PIN_INPUT, 7) /* (AD38) MCASP1_AXR0.GPIO0_48 */ |
| J784S4_IOPAD(0x00C, PIN_INPUT, 7) /* (AF33) MCAN13_TX.GPIO0_3 */ |
| J784S4_IOPAD(0x0B8, PIN_INPUT, 7) /* (AC34) MCASP1_ACLKX.GPIO0_46 */ |
| J784S4_IOPAD(0x090, PIN_INPUT, 7) /* (AC35) MCASP0_AXR8.GPIO0_36 */ |
| J784S4_IOPAD(0x0A8, PIN_INPUT, 7) /* (AF34) MCASP0_AXR14.GPIO0_42 */ |
| J784S4_IOPAD(0x0A4, PIN_INPUT, 7) /* (AJ36) MCASP0_AXR13.GPIO0_41 */ |
| J784S4_IOPAD(0x034, PIN_INPUT, 7) /* (AJ34) PMIC_WAKE0n.GPIO0_13 */ |
| J784S4_IOPAD(0x0CC, PIN_INPUT, 7) /* (AM37) SPI0_CS0.GPIO0_51 */ |
| J784S4_IOPAD(0x08C, PIN_INPUT, 7) /* (AE35) MCASP0_AXR7.GPIO0_35 */ |
| J784S4_IOPAD(0x008, PIN_INPUT, 7) /* (AJ33) MCAN12_RX.GPIO0_2 */ |
| J784S4_IOPAD(0x004, PIN_INPUT, 7) /* (AG36) MCAN12_TX.GPIO0_1 */ |
| >; |
| }; |
| |
| dp0_pins_default: dp0-default-pins { |
| pinctrl-single,pins = < |
| J784S4_IOPAD(0x014, PIN_INPUT, 13) /* (AG33) MCAN14_TX.DP0_HPD */ |
| >; |
| }; |
| |
| dp_pwr_en_pins_default: dp-pwr-en-default-pins { |
| pinctrl-single,pins = < |
| J784S4_IOPAD(0x010, PIN_INPUT, 7) /* (AH33) MCAN13_RX.GPIO0_4 */ |
| >; |
| }; |
| |
| dss_vout0_pins_default: dss-vout0-default-pins { |
| pinctrl-single,pins = < |
| J784S4_IOPAD(0x074, PIN_OUTPUT, 2) /* (AC33) MCAN2_TX.VOUT0_DATA0 */ |
| J784S4_IOPAD(0x070, PIN_OUTPUT, 2) /* (AH38) MCAN1_RX.VOUT0_DATA1 */ |
| J784S4_IOPAD(0x07c, PIN_OUTPUT, 2) /* (AJ38) MCASP0_AXR3.VOUT0_DATA2 */ |
| J784S4_IOPAD(0x068, PIN_OUTPUT, 2) /* (AE38) MCAN0_RX.VOUT0_DATA3 */ |
| J784S4_IOPAD(0x064, PIN_OUTPUT, 2) /* (AF38) MCAN0_TX.VOUT0_DATA4 */ |
| J784S4_IOPAD(0x060, PIN_OUTPUT, 2) /* (AE36) MCASP2_AXR1.VOUT0_DATA5 */ |
| J784S4_IOPAD(0x05c, PIN_OUTPUT, 2) /* (AC36) MCASP2_AXR0.VOUT0_DATA6 */ |
| J784S4_IOPAD(0x058, PIN_OUTPUT, 2) /* (AE37) MCASP2_AFSX.VOUT0_DATA7 */ |
| J784S4_IOPAD(0x054, PIN_OUTPUT, 2) /* (AD37) MCASP2_ACLKX.VOUT0_DATA8 */ |
| J784S4_IOPAD(0x050, PIN_OUTPUT, 2) /* (AC37) MCASP1_AXR2.VOUT0_DATA9 */ |
| J784S4_IOPAD(0x04c, PIN_OUTPUT, 2) /* (AC32) MCASP1_AXR1.VOUT0_DATA10 */ |
| J784S4_IOPAD(0x048, PIN_OUTPUT, 2) /* (AK33) MCASP0_AXR2.VOUT0_DATA11 */ |
| J784S4_IOPAD(0x044, PIN_OUTPUT, 2) /* (AG37) MCASP0_AXR1.VOUT0_DATA12 */ |
| J784S4_IOPAD(0x040, PIN_OUTPUT, 2) /* (AF37) MCASP0_AXR0.VOUT0_DATA13 */ |
| J784S4_IOPAD(0x03c, PIN_OUTPUT, 2) /* (AK38) MCASP0_AFSX.VOUT0_DATA14 */ |
| J784S4_IOPAD(0x038, PIN_OUTPUT, 2) /* (AK35) MCASP0_ACLKX.VOUT0_DATA15 */ |
| J784S4_IOPAD(0x0c8, PIN_OUTPUT, 2) /* (AJ32) EXT_REFCLK1.VOUT0_DATA16 */ |
| J784S4_IOPAD(0x030, PIN_OUTPUT, 2) /* (AK37) GPIO0_12.VOUT0_DATA17 */ |
| J784S4_IOPAD(0x02c, PIN_OUTPUT, 2) /* (AL32) GPIO0_11.VOUT0_DATA18 */ |
| J784S4_IOPAD(0x028, PIN_OUTPUT, 2) /* (AE33) MCAN16_RX.VOUT0_DATA19 */ |
| J784S4_IOPAD(0x024, PIN_OUTPUT, 2) /* (AH34) MCAN16_TX.VOUT0_DATA20 */ |
| J784S4_IOPAD(0x020, PIN_OUTPUT, 2) /* (AJ35) MCAN15_RX.VOUT0_DATA21 */ |
| J784S4_IOPAD(0x01c, PIN_OUTPUT, 2) /* (AG34) MCAN15_TX.VOUT0_DATA22 */ |
| J784S4_IOPAD(0x018, PIN_OUTPUT, 2) /* (AK36) MCAN14_RX.VOUT0_DATA23 */ |
| J784S4_IOPAD(0x084, PIN_OUTPUT, 2) /* (AG38) MCASP0_AXR5.VOUT0_DE */ |
| J784S4_IOPAD(0x080, PIN_OUTPUT, 2) /* (AK34) MCASP0_AXR4.VOUT0_HSYNC */ |
| J784S4_IOPAD(0x078, PIN_OUTPUT, 2) /* (AH37) MCAN2_RX.VOUT0_PCLK */ |
| J784S4_IOPAD(0x088, PIN_OUTPUT, 2) /* (AF36) MCASP0_AXR6.VOUT0_VSYNC */ |
| >; |
| }; |
| |
| hdmi_hpd_pins_default: hdmi-hpd-default-pins { |
| pinctrl-single,pins = < |
| J784S4_IOPAD(0x000, PIN_INPUT, 7) /* (AN35) EXTINTN.GPIO0_0 */ |
| >; |
| }; |
| |
| main_mcan6_pins_default: main-mcan6-default-pins { |
| pinctrl-single,pins = < |
| J784S4_IOPAD(0x098, PIN_INPUT, 0) /* (AH36) MCAN6_RX */ |
| J784S4_IOPAD(0x094, PIN_OUTPUT, 0) /* (AG35) MCAN6_TX */ |
| >; |
| }; |
| |
| main_mcan7_pins_default: main-mcan7-default-pins { |
| pinctrl-single,pins = < |
| J784S4_IOPAD(0x0A0, PIN_INPUT, 0) /* (AD34) MCAN7_RX */ |
| J784S4_IOPAD(0x09C, PIN_OUTPUT, 0) /* (AF35) MCAN7_TX */ |
| >; |
| }; |
| |
| }; |
| |
| &wkup_pmx0 { |
| bootph-all; |
| mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { |
| pinctrl-single,pins = < |
| J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (E32) MCU_OSPI0_CLK */ |
| J784S4_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (A32) MCU_OSPI0_CSn0 */ |
| J784S4_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B33) MCU_OSPI0_D0 */ |
| J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B32) MCU_OSPI0_D1 */ |
| J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (C33) MCU_OSPI0_D2 */ |
| J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (C35) MCU_OSPI0_D3 */ |
| J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (D33) MCU_OSPI0_D4 */ |
| J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D34) MCU_OSPI0_D5 */ |
| J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (E34) MCU_OSPI0_D6 */ |
| J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (E33) MCU_OSPI0_D7 */ |
| J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (C34) MCU_OSPI0_DQS */ |
| >; |
| }; |
| }; |
| |
| &wkup_pmx2 { |
| bootph-all; |
| pmic_irq_pins_default: pmic-irq-default-pins { |
| pinctrl-single,pins = < |
| /* (AA37) MCU_ADC1_AIN4.WKUP_GPIO0_83 */ |
| J784S4_WKUP_IOPAD(0x0fc, PIN_INPUT, 7) |
| >; |
| }; |
| |
| wkup_uart0_pins_default: wkup-uart0-default-pins { |
| bootph-all; |
| pinctrl-single,pins = < |
| J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (L37) WKUP_GPIO0_6.WKUP_UART0_CTSn */ |
| J721S2_WKUP_IOPAD(0x074, PIN_INPUT, 0) /* (L36) WKUP_GPIO0_7.WKUP_UART0_RTSn */ |
| J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (K35) WKUP_UART0_RXD */ |
| J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (K34) WKUP_UART0_TXD */ |
| >; |
| }; |
| |
| wkup_i2c0_pins_default: wkup-i2c0-default-pins { |
| bootph-all; |
| pinctrl-single,pins = < |
| J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */ |
| J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */ |
| >; |
| }; |
| |
| mcu_uart0_pins_default: mcu-uart0-default-pins { |
| bootph-all; |
| pinctrl-single,pins = < |
| J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (K38) WKUP_GPIO0_13.MCU_UART0_RXD */ |
| J784S4_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (J37) WKUP_GPIO0_12.MCU_UART0_TXD */ |
| >; |
| }; |
| |
| mcu_i2c0_pins_default: mcu-i2c0-default-pins { |
| pinctrl-single,pins = < |
| J784S4_WKUP_IOPAD(0x0a0, PIN_INPUT_PULLUP, 0) /* (M35) MCU_I2C0_SCL */ |
| J784S4_WKUP_IOPAD(0x0a4, PIN_INPUT_PULLUP, 0) /* (G34) MCU_I2C0_SDA */ |
| >; |
| }; |
| |
| mcu_cpsw_pins_default: mcu-cpsw-default-pins { |
| pinctrl-single,pins = < |
| J784S4_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */ |
| J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B36) MCU_RGMII1_RD1 */ |
| J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C36) MCU_RGMII1_RD2 */ |
| J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D36) MCU_RGMII1_RD3 */ |
| J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (B37) MCU_RGMII1_RXC */ |
| J784S4_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (C37) MCU_RGMII1_RX_CTL */ |
| J784S4_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (D37) MCU_RGMII1_TD0 */ |
| J784S4_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (D38) MCU_RGMII1_TD1 */ |
| J784S4_WKUP_IOPAD(0x00c, PIN_OUTPUT, 0) /* (E37) MCU_RGMII1_TD2 */ |
| J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E38) MCU_RGMII1_TD3 */ |
| J784S4_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (E36) MCU_RGMII1_TXC */ |
| J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (C38) MCU_RGMII1_TX_CTL */ |
| >; |
| }; |
| |
| mcu_mdio_pins_default: mcu-mdio-default-pins { |
| pinctrl-single,pins = < |
| J784S4_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */ |
| J784S4_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */ |
| >; |
| }; |
| |
| mcu_rpi_hdr1_gpio0_pins_default: mcu-rpi-hdr1-gpio0-default-pins { |
| pinctrl-single,pins = < |
| J784S4_WKUP_IOPAD(0x118, PIN_INPUT, 7) /* (N34) WKUP_GPIO0_66 */ |
| J784S4_WKUP_IOPAD(0x05c, PIN_INPUT, 7) /* (J34) WKUP_GPIO0_1 */ |
| J784S4_WKUP_IOPAD(0x060, PIN_INPUT, 7) /* (J35) WKUP_GPIO0_2 */ |
| J784S4_WKUP_IOPAD(0x058, PIN_INPUT, 7) /* (H38) WKUP_GPIO0_0 */ |
| J784S4_WKUP_IOPAD(0x0b8, PIN_INPUT, 7) /* (M37) WKUP_GPIO0_56 */ |
| J784S4_WKUP_IOPAD(0x114, PIN_INPUT, 7) /* (M36) WKUP_GPIO0_57 */ |
| J784S4_WKUP_IOPAD(0x094, PIN_INPUT, 7) /* (K37) WKUP_GPIO0_15 */ |
| J784S4_WKUP_IOPAD(0x064, PIN_INPUT, 7) /* (J36) WKUP_GPIO0_3 */ |
| J784S4_WKUP_IOPAD(0x11c, PIN_INPUT, 7) /* (M34) WKUP_GPIO0_67 */ |
| >; |
| }; |
| |
| mcu_i2c1_pins_default: mcu-i2c1-default-pins { |
| pinctrl-single,pins = < |
| /* (L35) WKUP_GPIO0_8.MCU_I2C1_SCL */ |
| J784S4_WKUP_IOPAD(0x078, PIN_INPUT_PULLUP, 0) |
| /* (L34) WKUP_GPIO0_9.MCU_I2C1_SDA */ |
| J784S4_WKUP_IOPAD(0x07c, PIN_INPUT_PULLUP, 0) |
| >; |
| }; |
| |
| hdmi_pdn_pins_default: hdmi-pdn-default-pins { |
| pinctrl-single,pins = < |
| J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 7) /* (H37) WKUP_GPIO0_14 */ |
| >; |
| }; |
| |
| mcu_mcan0_pins_default: mcu-mcan0-default-pins { |
| pinctrl-single,pins = < |
| J784S4_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (F38) MCU_MCAN0_RX */ |
| J784S4_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (K33) MCU_MCAN0_TX */ |
| >; |
| }; |
| |
| mcu_mcan1_pins_default: mcu-mcan1-default-pins { |
| pinctrl-single,pins = < |
| J784S4_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (K36) WKUP_GPIO0_5.MCU_MCAN1_RX */ |
| J784S4_WKUP_IOPAD(0x068, PIN_OUTPUT, 0)/* (H35) WKUP_GPIO0_4.MCU_MCAN1_TX */ |
| >; |
| }; |
| |
| }; |
| |
| &wkup_pmx3 { |
| mcu_rpi_hdr2_gpio0_pins_default: mcu-rpi-hdr2-gpio0-default-pins { |
| pinctrl-single,pins = < |
| J784S4_WKUP_IOPAD(0x0, PIN_INPUT, 7) /* (M33) WKUP_GPIO0_49 */ |
| >; |
| }; |
| }; |
| |
| &mailbox0_cluster0 { |
| status = "okay"; |
| interrupts = <436>; |
| mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { |
| ti,mbox-rx = <0 0 0>; |
| ti,mbox-tx = <1 0 0>; |
| }; |
| |
| mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { |
| ti,mbox-rx = <2 0 0>; |
| ti,mbox-tx = <3 0 0>; |
| }; |
| }; |
| |
| &mailbox0_cluster1 { |
| status = "okay"; |
| interrupts = <432>; |
| mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { |
| ti,mbox-rx = <0 0 0>; |
| ti,mbox-tx = <1 0 0>; |
| }; |
| |
| mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { |
| ti,mbox-rx = <2 0 0>; |
| ti,mbox-tx = <3 0 0>; |
| }; |
| }; |
| |
| &mailbox0_cluster2 { |
| status = "okay"; |
| interrupts = <428>; |
| mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { |
| ti,mbox-rx = <0 0 0>; |
| ti,mbox-tx = <1 0 0>; |
| }; |
| |
| mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { |
| ti,mbox-rx = <2 0 0>; |
| ti,mbox-tx = <3 0 0>; |
| }; |
| }; |
| |
| &mailbox0_cluster3 { |
| status = "okay"; |
| interrupts = <424>; |
| mbox_main_r5fss2_core0: mbox-main-r5fss2-core0 { |
| ti,mbox-rx = <0 0 0>; |
| ti,mbox-tx = <1 0 0>; |
| }; |
| |
| mbox_main_r5fss2_core1: mbox-main-r5fss2-core1 { |
| ti,mbox-rx = <2 0 0>; |
| ti,mbox-tx = <3 0 0>; |
| }; |
| }; |
| |
| &mailbox0_cluster4 { |
| status = "okay"; |
| interrupts = <420>; |
| mbox_c71_0: mbox-c71-0 { |
| ti,mbox-rx = <0 0 0>; |
| ti,mbox-tx = <1 0 0>; |
| }; |
| |
| mbox_c71_1: mbox-c71-1 { |
| ti,mbox-rx = <2 0 0>; |
| ti,mbox-tx = <3 0 0>; |
| }; |
| }; |
| |
| &mailbox0_cluster5 { |
| status = "okay"; |
| interrupts = <416>; |
| mbox_c71_2: mbox-c71-2 { |
| ti,mbox-rx = <0 0 0>; |
| ti,mbox-tx = <1 0 0>; |
| }; |
| |
| mbox_c71_3: mbox-c71-3 { |
| ti,mbox-rx = <2 0 0>; |
| ti,mbox-tx = <3 0 0>; |
| }; |
| }; |
| |
| &wkup_uart0 { |
| /* Firmware usage */ |
| status = "reserved"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&wkup_uart0_pins_default>; |
| }; |
| |
| &wkup_i2c0 { |
| bootph-all; |
| status = "okay"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&wkup_i2c0_pins_default>; |
| clock-frequency = <400000>; |
| |
| eeprom@51 { |
| /* AT24C512C-MAHM-T */ |
| compatible = "atmel,24c512"; |
| reg = <0x51>; |
| }; |
| |
| tps659413: pmic@48 { |
| compatible = "ti,tps6594-q1"; |
| reg = <0x48>; |
| system-power-controller; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pmic_irq_pins_default>; |
| interrupt-parent = <&wkup_gpio0>; |
| interrupts = <83 IRQ_TYPE_EDGE_FALLING>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| ti,primary-pmic; |
| buck12-supply = <&vsys_3v3>; |
| buck3-supply = <&vsys_3v3>; |
| buck4-supply = <&vsys_3v3>; |
| buck5-supply = <&vsys_3v3>; |
| ldo1-supply = <&vsys_3v3>; |
| ldo2-supply = <&vsys_3v3>; |
| ldo3-supply = <&vsys_3v3>; |
| ldo4-supply = <&vsys_3v3>; |
| |
| regulators { |
| bucka12: buck12 { |
| regulator-name = "vdd_ddr_1v1"; |
| regulator-min-microvolt = <1100000>; |
| regulator-max-microvolt = <1100000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| bucka3: buck3 { |
| regulator-name = "vdd_ram_0v85"; |
| regulator-min-microvolt = <850000>; |
| regulator-max-microvolt = <850000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| bucka4: buck4 { |
| regulator-name = "vdd_io_1v8"; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <1800000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| bucka5: buck5 { |
| regulator-name = "vdd_mcu_0v85"; |
| regulator-min-microvolt = <850000>; |
| regulator-max-microvolt = <850000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| ldoa1: ldo1 { |
| regulator-name = "vdd_mcuio_1v8"; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <1800000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| ldoa2: ldo2 { |
| regulator-name = "vdd_mcuio_3v3"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| ldoa3: ldo3 { |
| regulator-name = "vds_dll_0v8"; |
| regulator-min-microvolt = <800000>; |
| regulator-max-microvolt = <800000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| ldoa4: ldo4 { |
| regulator-name = "vda_mcu_1v8"; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <1800000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| }; |
| }; |
| }; |
| |
| &wkup_gpio0 { |
| status = "okay"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&mcu_rpi_hdr1_gpio0_pins_default>, <&mcu_rpi_hdr2_gpio0_pins_default>; |
| }; |
| |
| &mcu_uart0 { |
| bootph-all; |
| status = "okay"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&mcu_uart0_pins_default>; |
| }; |
| |
| &mcu_i2c0 { |
| status = "okay"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&mcu_i2c0_pins_default>; |
| clock-frequency = <400000>; |
| }; |
| |
| &main_uart8 { |
| bootph-all; |
| status = "okay"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&main_uart8_pins_default>; |
| }; |
| |
| &main_i2c0 { |
| status = "okay"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&main_i2c0_pins_default>; |
| clock-frequency = <400000>; |
| |
| exp1: gpio@21 { |
| compatible = "ti,tca6416"; |
| reg = <0x21>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-line-names = "BOARDID_EEPROM_WP", "CAN_STB", "GPIO_uSD_PWR_EN", |
| "IO_EXP_MCU_RGMII_RST#", "IO_EXP_PCIe0_4L_PERST#", |
| "IO_EXP_PCIe1_M.2_RTSz", "IO_EXP_PCIe3_M.2_RTSz", |
| "PM_INA_BUS_EN", "ENET1_EXP_PWRDN", "EXP1_ENET_RSTz", |
| "ENET1_I2CMUX_SEL", "PCIe0_CLKREQ#", "PCIe1_M.2_CLKREQ#", |
| "PCIe3_M2_CLKREQ#", "PCIe0_PRSNT2#_1", "PCIe0_PRSNT2#_2"; |
| }; |
| }; |
| |
| &main_i2c1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&main_i2c1_pins_default>; |
| clock-frequency = <400000>; |
| status = "okay"; |
| |
| exp2: gpio@21 { |
| compatible = "ti,tca6408"; |
| reg = <0x21>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-line-names = "CSI_VIO_SEL", "CSI_MUX_SEL_2", "CSI2_RSTz", |
| "IO_EXP_CAM0_GPIO1", "IO_EXP_CAM1_GPIO1"; |
| }; |
| |
| i2c-mux@70 { |
| compatible = "nxp,pca9543"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x70>; |
| |
| cam0_i2c: i2c@0 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0>; |
| }; |
| |
| cam1_i2c: i2c@1 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <1>; |
| }; |
| |
| }; |
| }; |
| |
| &main_sdhci0 { |
| bootph-all; |
| /* eMMC */ |
| status = "okay"; |
| non-removable; |
| ti,driver-strength-ohm = <50>; |
| disable-wp; |
| }; |
| |
| &main_sdhci1 { |
| bootph-all; |
| /* SD card */ |
| status = "okay"; |
| pinctrl-0 = <&main_mmc1_pins_default>; |
| pinctrl-names = "default"; |
| disable-wp; |
| vmmc-supply = <&vdd_mmc1>; |
| vqmmc-supply = <&vdd_sd_dv>; |
| }; |
| |
| &main_gpio0 { |
| status = "okay"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&rpi_header_gpio0_pins_default>; |
| }; |
| |
| &mcu_cpsw { |
| status = "okay"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; |
| }; |
| |
| &davinci_mdio { |
| mcu_phy0: ethernet-phy@0 { |
| reg = <0>; |
| ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; |
| ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; |
| ti,min-output-impedance; |
| }; |
| }; |
| |
| &mcu_cpsw_port1 { |
| status = "okay"; |
| phy-mode = "rgmii-rxid"; |
| phy-handle = <&mcu_phy0>; |
| }; |
| |
| &mcu_r5fss0_core0 { |
| mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; |
| memory-region = <&mcu_r5fss0_core0_dma_memory_region>, |
| <&mcu_r5fss0_core0_memory_region>; |
| }; |
| |
| &mcu_r5fss0_core1 { |
| mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; |
| memory-region = <&mcu_r5fss0_core1_dma_memory_region>, |
| <&mcu_r5fss0_core1_memory_region>; |
| }; |
| |
| &main_r5fss0_core0 { |
| mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; |
| memory-region = <&main_r5fss0_core0_dma_memory_region>, |
| <&main_r5fss0_core0_memory_region>; |
| }; |
| |
| &main_r5fss0_core1 { |
| mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; |
| memory-region = <&main_r5fss0_core1_dma_memory_region>, |
| <&main_r5fss0_core1_memory_region>; |
| }; |
| |
| &main_r5fss1_core0 { |
| mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; |
| memory-region = <&main_r5fss1_core0_dma_memory_region>, |
| <&main_r5fss1_core0_memory_region>; |
| }; |
| |
| &main_r5fss1_core1 { |
| mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; |
| memory-region = <&main_r5fss1_core1_dma_memory_region>, |
| <&main_r5fss1_core1_memory_region>; |
| }; |
| |
| &main_r5fss2_core0 { |
| mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core0>; |
| memory-region = <&main_r5fss2_core0_dma_memory_region>, |
| <&main_r5fss2_core0_memory_region>; |
| }; |
| |
| &main_r5fss2_core1 { |
| mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core1>; |
| memory-region = <&main_r5fss2_core1_dma_memory_region>, |
| <&main_r5fss2_core1_memory_region>; |
| }; |
| |
| &c71_0 { |
| status = "okay"; |
| mboxes = <&mailbox0_cluster4 &mbox_c71_0>; |
| memory-region = <&c71_0_dma_memory_region>, |
| <&c71_0_memory_region>; |
| }; |
| |
| &c71_1 { |
| status = "okay"; |
| mboxes = <&mailbox0_cluster4 &mbox_c71_1>; |
| memory-region = <&c71_1_dma_memory_region>, |
| <&c71_1_memory_region>; |
| }; |
| |
| &c71_2 { |
| status = "okay"; |
| mboxes = <&mailbox0_cluster5 &mbox_c71_2>; |
| memory-region = <&c71_2_dma_memory_region>, |
| <&c71_2_memory_region>; |
| }; |
| |
| &c71_3 { |
| status = "okay"; |
| mboxes = <&mailbox0_cluster5 &mbox_c71_3>; |
| memory-region = <&c71_3_dma_memory_region>, |
| <&c71_3_memory_region>; |
| }; |
| |
| &wkup_gpio_intr { |
| status = "okay"; |
| }; |
| |
| &mcu_i2c1 { |
| status = "okay"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&mcu_i2c1_pins_default>; |
| clock-frequency = <100000>; |
| }; |
| |
| &serdes_refclk { |
| status = "okay"; |
| clock-frequency = <100000000>; |
| }; |
| |
| &dss { |
| status = "okay"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&dss_vout0_pins_default>; |
| assigned-clocks = <&k3_clks 218 2>, |
| <&k3_clks 218 5>; |
| assigned-clock-parents = <&k3_clks 218 3>, |
| <&k3_clks 218 7>; |
| }; |
| |
| &serdes_wiz4 { |
| status = "okay"; |
| }; |
| |
| &serdes4 { |
| status = "okay"; |
| serdes4_dp_link: phy@0 { |
| reg = <0>; |
| cdns,num-lanes = <4>; |
| #phy-cells = <0>; |
| cdns,phy-type = <PHY_TYPE_DP>; |
| resets = <&serdes_wiz4 1>, <&serdes_wiz4 2>, |
| <&serdes_wiz4 3>, <&serdes_wiz4 4>; |
| }; |
| }; |
| |
| &mhdp { |
| status = "okay"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&dp0_pins_default>; |
| phys = <&serdes4_dp_link>; |
| phy-names = "dpphy"; |
| }; |
| |
| &dss_ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| /* DP */ |
| port@0 { |
| reg = <0>; |
| |
| dpi0_out: endpoint { |
| remote-endpoint = <&dp0_in>; |
| }; |
| }; |
| |
| /* HDMI */ |
| port@1 { |
| reg = <1>; |
| |
| dpi1_out0: endpoint { |
| remote-endpoint = <&tfp410_in>; |
| }; |
| }; |
| }; |
| |
| &dp0_ports { |
| |
| port@0 { |
| reg = <0>; |
| |
| dp0_in: endpoint { |
| remote-endpoint = <&dpi0_out>; |
| }; |
| }; |
| |
| port@4 { |
| reg = <4>; |
| |
| dp0_out: endpoint { |
| remote-endpoint = <&dp0_connector_in>; |
| }; |
| }; |
| }; |
| |
| &mcu_mcan0 { |
| status = "okay"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&mcu_mcan0_pins_default>; |
| phys = <&transceiver1>; |
| }; |
| |
| &mcu_mcan1 { |
| status = "okay"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&mcu_mcan1_pins_default>; |
| phys = <&transceiver2>; |
| }; |
| |
| &main_mcan6 { |
| status = "okay"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&main_mcan6_pins_default>; |
| phys = <&transceiver3>; |
| }; |
| |
| &main_mcan7 { |
| status = "okay"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&main_mcan7_pins_default>; |
| phys = <&transceiver4>; |
| }; |
| |
| &ospi0 { |
| status = "okay"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; |
| |
| flash@0 { |
| compatible = "jedec,spi-nor"; |
| reg = <0x0>; |
| spi-tx-bus-width = <8>; |
| spi-rx-bus-width = <8>; |
| spi-max-frequency = <25000000>; |
| cdns,tshsl-ns = <60>; |
| cdns,tsd2d-ns = <60>; |
| cdns,tchsh-ns = <60>; |
| cdns,tslch-ns = <60>; |
| cdns,read-delay = <4>; |
| |
| partitions { |
| bootph-all; |
| compatible = "fixed-partitions"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| partition@0 { |
| label = "ospi.tiboot3"; |
| reg = <0x0 0x100000>; |
| }; |
| |
| partition@100000 { |
| label = "ospi.tispl"; |
| reg = <0x100000 0x200000>; |
| }; |
| |
| partition@300000 { |
| label = "ospi.u-boot"; |
| reg = <0x300000 0x400000>; |
| }; |
| |
| partition@700000 { |
| label = "ospi.env"; |
| reg = <0x700000 0x40000>; |
| }; |
| |
| partition@740000 { |
| label = "ospi.env.backup"; |
| reg = <0x740000 0x40000>; |
| }; |
| |
| partition@800000 { |
| label = "ospi.rootfs"; |
| reg = <0x800000 0x37c0000>; |
| }; |
| |
| partition@3fc0000 { |
| bootph-pre-ram; |
| label = "ospi.phypattern"; |
| reg = <0x3fc0000 0x40000>; |
| }; |
| }; |
| }; |
| }; |
