| // SPDX-License-Identifier: GPL-2.0+ |
| /* |
| * dts file for Xilinx ZynqMP ZCU102 RevB |
| * |
| * (C) Copyright 2016 - 2022, Xilinx, Inc. |
| * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. |
| * |
| * Michal Simek <michal.simek@amd.com> |
| */ |
| |
| #include "zynqmp-zcu102-revA.dts" |
| |
| / { |
| model = "ZynqMP ZCU102 RevB"; |
| compatible = "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; |
| }; |
| |
| &gem3 { |
| phy-handle = <&phyc>; |
| mdio: mdio { |
| phyc: ethernet-phy@c { |
| #phy-cells = <0x1>; |
| compatible = "ethernet-phy-id2000.a231"; |
| reg = <0xc>; |
| ti,rx-internal-delay = <0x8>; |
| ti,tx-internal-delay = <0xa>; |
| ti,fifo-depth = <0x1>; |
| ti,dp83867-rxctrl-strap-quirk; |
| reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; |
| }; |
| /* Cleanup from RevA */ |
| /delete-node/ ethernet-phy@21; |
| }; |
| }; |
| |
| /* Fix collision with u61 */ |
| &i2c0 { |
| i2c-mux@75 { |
| i2c@2 { |
| max15303@1b { /* u8 */ |
| compatible = "maxim,max15303"; |
| reg = <0x1b>; |
| }; |
| /delete-node/ max15303@20; |
| }; |
| }; |
| }; |
