arch/arm/boot/dts/bcm-cygnus.dtsi - linux - Git at Google

 /*
  *  BSD LICENSE
  *
  *  Copyright(c) 2014 Broadcom Corporation.  All rights reserved.
  *
  *  Redistribution and use in source and binary forms, with or without
  *  modification, are permitted provided that the following conditions
  *  are met:
  *
  *    * Redistributions of source code must retain the above copyright
  *      notice, this list of conditions and the following disclaimer.
  *    * Redistributions in binary form must reproduce the above copyright
  *      notice, this list of conditions and the following disclaimer in
  *      the documentation and/or other materials provided with the
  *      distribution.
  *    * Neither the name of Broadcom Corporation nor the names of its
  *      contributors may be used to endorse or promote products derived
  *      from this software without specific prior written permission.
  *
  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */

 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/clock/bcm-cygnus.h>

 #include "skeleton.dtsi"

 / {
 	compatible = "brcm,cygnus";
 	model = "Broadcom Cygnus SoC";
 	interrupt-parent = <&gic>;

 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;

 		cpu@0 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a9";
 			next-level-cache = <&L2>;
 			reg = <0x0>;
 		};
 	};

 	/include/ "bcm-cygnus-clock.dtsi"

 	core {
 		compatible = "simple-bus";
 		ranges = <0x00000000 0x19000000 0x1000000>;
 		#address-cells = <1>;
 		#size-cells = <1>;

 		timer@20200 {
 			compatible = "arm,cortex-a9-global-timer";
 			reg = <0x20200 0x100>;
 			interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&periph_clk>;
 		};

 		gic: interrupt-controller@21000 {
 			compatible = "arm,cortex-a9-gic";
 			#interrupt-cells = <3>;
 			#address-cells = <0>;
 			interrupt-controller;
 			reg = <0x21000 0x1000>,
 			      <0x20100 0x100>;
 		};

 		L2: l2-cache {
 			compatible = "arm,pl310-cache";
 			reg = <0x22000 0x1000>;
 			cache-unified;
 			cache-level = <2>;
 		};
 	};

 	axi {
 		compatible = "simple-bus";
 		ranges;
 		#address-cells = <1>;
 		#size-cells = <1>;

 		pcie_phy: phy@0301d0a0 {
 			compatible = "brcm,cygnus-pcie-phy";
 			reg = <0x0301d0a0 0x14>;
 			#address-cells = <1>;
 			#size-cells = <0>;

 			pcie0_phy: phy@0 {
 				reg = <0>;
 				#phy-cells = <0>;
 			};

 			pcie1_phy: phy@1 {
 				reg = <1>;
 				#phy-cells = <0>;
 			};
 		};

 		pinctrl: pinctrl@0x0301d0c8 {
 			compatible = "brcm,cygnus-pinmux";
 			reg = <0x0301d0c8 0x30>,
 			      <0x0301d24c 0x2c>;
 		};

 		gpio_crmu: gpio@03024800 {
 			compatible = "brcm,cygnus-crmu-gpio";
 			reg = <0x03024800 0x50>,
 			      <0x03024008 0x18>;
 			ngpios = <6>;
 			#gpio-cells = <2>;
 			gpio-controller;
 		};

 		i2c0: i2c@18008000 {
 			compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c";
 			reg = <0x18008000 0x100>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			interrupts = <GIC_SPI 85 IRQ_TYPE_NONE>;
 			clock-frequency = <100000>;
 			status = "disabled";
 		};

 		wdt0: wdt@18009000 {
 			compatible = "arm,sp805" , "arm,primecell";
 			reg = <0x18009000 0x1000>;
 			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&axi81_clk>;
 			clock-names = "apb_pclk";
 		};

 		gpio_ccm: gpio@1800a000 {
 			compatible = "brcm,cygnus-ccm-gpio";
 			reg = <0x1800a000 0x50>,
 			      <0x0301d164 0x20>;
 			ngpios = <24>;
 			#gpio-cells = <2>;
 			gpio-controller;
 			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-controller;
 		};

 		i2c1: i2c@1800b000 {
 			compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c";
 			reg = <0x1800b000 0x100>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			interrupts = <GIC_SPI 86 IRQ_TYPE_NONE>;
 			clock-frequency = <100000>;
 			status = "disabled";
 		};

 		pcie0: pcie@18012000 {
 			compatible = "brcm,iproc-pcie";
 			reg = <0x18012000 0x1000>;

 			#interrupt-cells = <1>;
 			interrupt-map-mask = <0 0 0 0>;
 			interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_NONE>;

 			linux,pci-domain = <0>;

 			bus-range = <0x00 0xff>;

 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";
 			ranges = <0x81000000 0 0	  0x28000000 0 0x00010000
 				  0x82000000 0 0x20000000 0x20000000 0 0x04000000>;

 			phys = <&pcie0_phy>;
 			phy-names = "pcie-phy";

 			status = "disabled";

 			msi-parent = <&msi0>;
 			msi0: msi@18012000 {
 				compatible = "brcm,iproc-msi";
 				msi-controller;
 				interrupt-parent = <&gic>;
 				interrupts = <GIC_SPI 96 IRQ_TYPE_NONE>,
 					     <GIC_SPI 97 IRQ_TYPE_NONE>,
 					     <GIC_SPI 98 IRQ_TYPE_NONE>,
 					     <GIC_SPI 99 IRQ_TYPE_NONE>;
 			};
 		};

 		pcie1: pcie@18013000 {
 			compatible = "brcm,iproc-pcie";
 			reg = <0x18013000 0x1000>;

 			#interrupt-cells = <1>;
 			interrupt-map-mask = <0 0 0 0>;
 			interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_NONE>;

 			linux,pci-domain = <1>;

 			bus-range = <0x00 0xff>;

 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";
 			ranges = <0x81000000 0 0	  0x48000000 0 0x00010000
 				  0x82000000 0 0x40000000 0x40000000 0 0x04000000>;

 			phys = <&pcie1_phy>;
 			phy-names = "pcie-phy";

 			status = "disabled";

 			msi-parent = <&msi1>;
 			msi1: msi@18013000 {
 				compatible = "brcm,iproc-msi";
 				msi-controller;
 				interrupt-parent = <&gic>;
 				interrupts = <GIC_SPI 102 IRQ_TYPE_NONE>,
 					     <GIC_SPI 103 IRQ_TYPE_NONE>,
 					     <GIC_SPI 104 IRQ_TYPE_NONE>,
 					     <GIC_SPI 105 IRQ_TYPE_NONE>;
 			};
 		};

 		uart0: serial@18020000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x18020000 0x100>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
 			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&axi81_clk>;
 			clock-frequency = <100000000>;
 			status = "disabled";
 		};

 		uart1: serial@18021000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x18021000 0x100>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
 			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&axi81_clk>;
 			clock-frequency = <100000000>;
 			status = "disabled";
 		};

 		uart2: serial@18022000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x18020000 0x100>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
 			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&axi81_clk>;
 			clock-frequency = <100000000>;
 			status = "disabled";
 		};

 		uart3: serial@18023000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x18023000 0x100>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
 			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&axi81_clk>;
 			clock-frequency = <100000000>;
 			status = "disabled";
 		};

 		nand: nand@18046000 {
 			compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
 			reg = <0x18046000 0x600>, <0xf8105408 0x600>,
 			      <0x18046f00 0x20>;
 			reg-names = "nand", "iproc-idm", "iproc-ext";
 			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;

 			#address-cells = <1>;
 			#size-cells = <0>;

 			brcm,nand-has-wp;
 		};

 		gpio_asiu: gpio@180a5000 {
 			compatible = "brcm,cygnus-asiu-gpio";
 			reg = <0x180a5000 0x668>;
 			ngpios = <146>;
 			#gpio-cells = <2>;
 			gpio-controller;

 			interrupt-controller;
 			interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
 			gpio-ranges = <&pinctrl 0 42 1>,
 					<&pinctrl 1 44 3>,
 					<&pinctrl 4 48 1>,
 					<&pinctrl 5 50 3>,
 					<&pinctrl 8 126 1>,
 					<&pinctrl 9 155 1>,
 					<&pinctrl 10 152 1>,
 					<&pinctrl 11 154 1>,
 					<&pinctrl 12 153 1>,
 					<&pinctrl 13 127 3>,
 					<&pinctrl 16 140 1>,
 					<&pinctrl 17 145 7>,
 					<&pinctrl 24 130 10>,
 					<&pinctrl 34 141 4>,
 					<&pinctrl 38 54 1>,
 					<&pinctrl 39 56 3>,
 					<&pinctrl 42 60 3>,
 					<&pinctrl 45 64 3>,
 					<&pinctrl 48 68 2>,
 					<&pinctrl 50 84 6>,
 					<&pinctrl 56 94 6>,
 					<&pinctrl 62 72 1>,
 					<&pinctrl 63 70 1>,
 					<&pinctrl 64 80 1>,
 					<&pinctrl 65 74 3>,
 					<&pinctrl 68 78 1>,
 					<&pinctrl 69 82 1>,
 					<&pinctrl 70 156 17>,
 					<&pinctrl 87 104 12>,
 					<&pinctrl 99 102 2>,
 					<&pinctrl 101 90 4>,
 					<&pinctrl 105 116 6>,
 					<&pinctrl 111 100 2>,
 					<&pinctrl 113 122 4>,
 					<&pinctrl 123 11 1>,
 					<&pinctrl 124 38 4>,
 					<&pinctrl 128 43 1>,
 					<&pinctrl 129 47 1>,
 					<&pinctrl 130 49 1>,
 					<&pinctrl 131 53 1>,
 					<&pinctrl 132 55 1>,
 					<&pinctrl 133 59 1>,
 					<&pinctrl 134 63 1>,
 					<&pinctrl 135 67 1>,
 					<&pinctrl 136 71 1>,
 					<&pinctrl 137 73 1>,
 					<&pinctrl 138 77 1>,
 					<&pinctrl 139 79 1>,
 					<&pinctrl 140 81 1>,
 					<&pinctrl 141 83 1>,
 					<&pinctrl 142 10 1>;
 		};

 		ts_adc_syscon: ts_adc_syscon@180a6000 {
 			compatible = "brcm,iproc-ts-adc-syscon", "syscon";
 			reg = <0x180a6000 0xc30>;
 		};

 		touchscreen: touchscreen@180a6000 {
 			compatible = "brcm,iproc-touchscreen";
 			#address-cells = <1>;
 			#size-cells = <1>;
 			ts_syscon = <&ts_adc_syscon>;
 			clocks = <&asiu_clks BCM_CYGNUS_ASIU_ADC_CLK>;
 			clock-names = "tsc_clk";
 			interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
 			status = "disabled";
 		};
 	};
 };
	/*
	* BSD LICENSE
	*
	* Copyright(c) 2014 Broadcom Corporation. All rights reserved.
	*
	* Redistribution and use in source and binary forms, with or without
	* modification, are permitted provided that the following conditions
	* are met:
	*
	* * Redistributions of source code must retain the above copyright
	* notice, this list of conditions and the following disclaimer.
	* * Redistributions in binary form must reproduce the above copyright
	* notice, this list of conditions and the following disclaimer in
	* the documentation and/or other materials provided with the
	* distribution.
	* * Neither the name of Broadcom Corporation nor the names of its
	* contributors may be used to endorse or promote products derived
	* from this software without specific prior written permission.
	*
	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
	* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
	* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
	* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
	* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
	* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
	* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	*/

	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/interrupt-controller/irq.h>
	#include <dt-bindings/clock/bcm-cygnus.h>

	#include "skeleton.dtsi"

	/ {
	compatible = "brcm,cygnus";
	model = "Broadcom Cygnus SoC";
	interrupt-parent = <&gic>;

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a9";
	next-level-cache = <&L2>;
	reg = <0x0>;
	};
	};

	/include/ "bcm-cygnus-clock.dtsi"

	core {
	compatible = "simple-bus";
	ranges = <0x00000000 0x19000000 0x1000000>;
	#address-cells = <1>;
	#size-cells = <1>;

	timer@20200 {
	compatible = "arm,cortex-a9-global-timer";
	reg = <0x20200 0x100>;
	interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&periph_clk>;
	};

	gic: interrupt-controller@21000 {
	compatible = "arm,cortex-a9-gic";
	#interrupt-cells = <3>;
	#address-cells = <0>;
	interrupt-controller;
	reg = <0x21000 0x1000>,
	<0x20100 0x100>;
	};

	L2: l2-cache {
	compatible = "arm,pl310-cache";
	reg = <0x22000 0x1000>;
	cache-unified;
	cache-level = <2>;
	};
	};

	axi {
	compatible = "simple-bus";
	ranges;
	#address-cells = <1>;
	#size-cells = <1>;

	pcie_phy: phy@0301d0a0 {
	compatible = "brcm,cygnus-pcie-phy";
	reg = <0x0301d0a0 0x14>;
	#address-cells = <1>;
	#size-cells = <0>;

	pcie0_phy: phy@0 {
	reg = <0>;
	#phy-cells = <0>;
	};

	pcie1_phy: phy@1 {
	reg = <1>;
	#phy-cells = <0>;
	};
	};

	pinctrl: pinctrl@0x0301d0c8 {
	compatible = "brcm,cygnus-pinmux";
	reg = <0x0301d0c8 0x30>,
	<0x0301d24c 0x2c>;
	};

	gpio_crmu: gpio@03024800 {
	compatible = "brcm,cygnus-crmu-gpio";
	reg = <0x03024800 0x50>,
	<0x03024008 0x18>;
	ngpios = <6>;
	#gpio-cells = <2>;
	gpio-controller;
	};

	i2c0: i2c@18008000 {
	compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c";
	reg = <0x18008000 0x100>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <GIC_SPI 85 IRQ_TYPE_NONE>;
	clock-frequency = <100000>;
	status = "disabled";
	};

	wdt0: wdt@18009000 {
	compatible = "arm,sp805" , "arm,primecell";
	reg = <0x18009000 0x1000>;
	interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&axi81_clk>;
	clock-names = "apb_pclk";
	};

	gpio_ccm: gpio@1800a000 {
	compatible = "brcm,cygnus-ccm-gpio";
	reg = <0x1800a000 0x50>,
	<0x0301d164 0x20>;
	ngpios = <24>;
	#gpio-cells = <2>;
	gpio-controller;
	interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-controller;
	};

	i2c1: i2c@1800b000 {
	compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c";
	reg = <0x1800b000 0x100>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <GIC_SPI 86 IRQ_TYPE_NONE>;
	clock-frequency = <100000>;
	status = "disabled";
	};

	pcie0: pcie@18012000 {
	compatible = "brcm,iproc-pcie";
	reg = <0x18012000 0x1000>;

	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 0 0>;
	interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_NONE>;

	linux,pci-domain = <0>;

	bus-range = <0x00 0xff>;

	#address-cells = <3>;
	#size-cells = <2>;
	device_type = "pci";
	ranges = <0x81000000 0 0 0x28000000 0 0x00010000
	0x82000000 0 0x20000000 0x20000000 0 0x04000000>;

	phys = <&pcie0_phy>;
	phy-names = "pcie-phy";

	status = "disabled";

	msi-parent = <&msi0>;
	msi0: msi@18012000 {
	compatible = "brcm,iproc-msi";
	msi-controller;
	interrupt-parent = <&gic>;
	interrupts = <GIC_SPI 96 IRQ_TYPE_NONE>,
	<GIC_SPI 97 IRQ_TYPE_NONE>,
	<GIC_SPI 98 IRQ_TYPE_NONE>,
	<GIC_SPI 99 IRQ_TYPE_NONE>;
	};
	};

	pcie1: pcie@18013000 {
	compatible = "brcm,iproc-pcie";
	reg = <0x18013000 0x1000>;

	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 0 0>;
	interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_NONE>;

	linux,pci-domain = <1>;

	bus-range = <0x00 0xff>;

	#address-cells = <3>;
	#size-cells = <2>;
	device_type = "pci";
	ranges = <0x81000000 0 0 0x48000000 0 0x00010000
	0x82000000 0 0x40000000 0x40000000 0 0x04000000>;

	phys = <&pcie1_phy>;
	phy-names = "pcie-phy";

	status = "disabled";

	msi-parent = <&msi1>;
	msi1: msi@18013000 {
	compatible = "brcm,iproc-msi";
	msi-controller;
	interrupt-parent = <&gic>;
	interrupts = <GIC_SPI 102 IRQ_TYPE_NONE>,
	<GIC_SPI 103 IRQ_TYPE_NONE>,
	<GIC_SPI 104 IRQ_TYPE_NONE>,
	<GIC_SPI 105 IRQ_TYPE_NONE>;
	};
	};

	uart0: serial@18020000 {
	compatible = "snps,dw-apb-uart";
	reg = <0x18020000 0x100>;
	reg-shift = <2>;
	reg-io-width = <4>;
	interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&axi81_clk>;
	clock-frequency = <100000000>;
	status = "disabled";
	};

	uart1: serial@18021000 {
	compatible = "snps,dw-apb-uart";
	reg = <0x18021000 0x100>;
	reg-shift = <2>;
	reg-io-width = <4>;
	interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&axi81_clk>;
	clock-frequency = <100000000>;
	status = "disabled";
	};

	uart2: serial@18022000 {
	compatible = "snps,dw-apb-uart";
	reg = <0x18020000 0x100>;
	reg-shift = <2>;
	reg-io-width = <4>;
	interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&axi81_clk>;
	clock-frequency = <100000000>;
	status = "disabled";
	};

	uart3: serial@18023000 {
	compatible = "snps,dw-apb-uart";
	reg = <0x18023000 0x100>;
	reg-shift = <2>;
	reg-io-width = <4>;
	interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&axi81_clk>;
	clock-frequency = <100000000>;
	status = "disabled";
	};

	nand: nand@18046000 {
	compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
	reg = <0x18046000 0x600>, <0xf8105408 0x600>,
	<0x18046f00 0x20>;
	reg-names = "nand", "iproc-idm", "iproc-ext";
	interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;

	#address-cells = <1>;
	#size-cells = <0>;

	brcm,nand-has-wp;
	};

	gpio_asiu: gpio@180a5000 {
	compatible = "brcm,cygnus-asiu-gpio";
	reg = <0x180a5000 0x668>;
	ngpios = <146>;
	#gpio-cells = <2>;
	gpio-controller;

	interrupt-controller;
	interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
	gpio-ranges = <&pinctrl 0 42 1>,
	<&pinctrl 1 44 3>,
	<&pinctrl 4 48 1>,
	<&pinctrl 5 50 3>,
	<&pinctrl 8 126 1>,
	<&pinctrl 9 155 1>,
	<&pinctrl 10 152 1>,
	<&pinctrl 11 154 1>,
	<&pinctrl 12 153 1>,
	<&pinctrl 13 127 3>,
	<&pinctrl 16 140 1>,
	<&pinctrl 17 145 7>,
	<&pinctrl 24 130 10>,
	<&pinctrl 34 141 4>,
	<&pinctrl 38 54 1>,
	<&pinctrl 39 56 3>,
	<&pinctrl 42 60 3>,
	<&pinctrl 45 64 3>,
	<&pinctrl 48 68 2>,
	<&pinctrl 50 84 6>,
	<&pinctrl 56 94 6>,
	<&pinctrl 62 72 1>,
	<&pinctrl 63 70 1>,
	<&pinctrl 64 80 1>,
	<&pinctrl 65 74 3>,
	<&pinctrl 68 78 1>,
	<&pinctrl 69 82 1>,
	<&pinctrl 70 156 17>,
	<&pinctrl 87 104 12>,
	<&pinctrl 99 102 2>,
	<&pinctrl 101 90 4>,
	<&pinctrl 105 116 6>,
	<&pinctrl 111 100 2>,
	<&pinctrl 113 122 4>,
	<&pinctrl 123 11 1>,
	<&pinctrl 124 38 4>,
	<&pinctrl 128 43 1>,
	<&pinctrl 129 47 1>,
	<&pinctrl 130 49 1>,
	<&pinctrl 131 53 1>,
	<&pinctrl 132 55 1>,
	<&pinctrl 133 59 1>,
	<&pinctrl 134 63 1>,
	<&pinctrl 135 67 1>,
	<&pinctrl 136 71 1>,
	<&pinctrl 137 73 1>,
	<&pinctrl 138 77 1>,
	<&pinctrl 139 79 1>,
	<&pinctrl 140 81 1>,
	<&pinctrl 141 83 1>,
	<&pinctrl 142 10 1>;
	};

	ts_adc_syscon: ts_adc_syscon@180a6000 {
	compatible = "brcm,iproc-ts-adc-syscon", "syscon";
	reg = <0x180a6000 0xc30>;
	};

	touchscreen: touchscreen@180a6000 {
	compatible = "brcm,iproc-touchscreen";
	#address-cells = <1>;
	#size-cells = <1>;
	ts_syscon = <&ts_adc_syscon>;
	clocks = <&asiu_clks BCM_CYGNUS_ASIU_ADC_CLK>;
	clock-names = "tsc_clk";
	interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};
	};
	};