Documentation/devicetree/bindings/mmc/hisilicon,hi3798cv200-dw-mshc.yaml

# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/mmc/hisilicon,hi3798cv200-dw-mshc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Hisilicon HiSTB SoCs specific extensions to the Synopsys DWMMC controller

maintainers:
  - Yang Xiwen <forbidden405@outlook.com>

properties:
  compatible:
    enum:
      - hisilicon,hi3798cv200-dw-mshc
      - hisilicon,hi3798mv200-dw-mshc

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    items:
      - description: bus interface unit clock
      - description: card interface unit clock
      - description: card input sample phase clock
      - description: controller output drive phase clock

  clock-names:
    items:
      - const: ciu
      - const: biu
      - const: ciu-sample
      - const: ciu-drive

  hisilicon,sap-dll-reg:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    description: |
      DWMMC core on Hi3798MV2x SoCs has a delay-locked-loop(DLL) attached to card data input path.
      It is integrated into CRG core on the SoC and has to be controlled during tuning.
    items:
      - description: A phandle pointed to the CRG syscon node
      - description: Sample DLL register offset in CRG address space

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names

allOf:
  - $ref: synopsys-dw-mshc-common.yaml#

  - if:
      properties:
        compatible:
          contains:
            const: hisilicon,hi3798mv200-dw-mshc
    then:
      required:
        - hisilicon,sap-dll-reg
    else:
      properties:
        hisilicon,sap-dll-reg: false

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/histb-clock.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    mmc@9830000 {
        compatible = "hisilicon,hi3798cv200-dw-mshc";
        reg = <0x9830000 0x10000>;
        interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&crg HISTB_MMC_CIU_CLK>,
                 <&crg HISTB_MMC_BIU_CLK>,
                 <&crg HISTB_MMC_SAMPLE_CLK>,
                 <&crg HISTB_MMC_DRV_CLK>;
        clock-names = "ciu", "biu", "ciu-sample", "ciu-drive";
        resets = <&crg 0xa0 4>;
        reset-names = "reset";
        pinctrl-names = "default";
        pinctrl-0 = <&emmc_pins_1 &emmc_pins_2
                     &emmc_pins_3 &emmc_pins_4>;
        fifo-depth = <256>;
        clock-frequency = <200000000>;
        cap-mmc-highspeed;
        mmc-ddr-1_8v;
        mmc-hs200-1_8v;
        non-removable;
        bus-width = <8>;
    };