| # SPDX-License-Identifier: GPL-2.0-only |
| # |
| # QE Communication options |
| # |
| |
| config QUICC_ENGINE |
| bool "QUICC Engine (QE) framework support" |
| depends on OF && HAS_IOMEM |
| depends on PPC || ARM || ARM64 || COMPILE_TEST |
| select GENERIC_ALLOCATOR |
| select CRC32 |
| help |
| The QUICC Engine (QE) is a new generation of communications |
| coprocessors on Freescale embedded CPUs (akin to CPM in older chips). |
| Selecting this option means that you wish to build a kernel |
| for a machine with a QE coprocessor. |
| |
| config UCC_SLOW |
| bool |
| default y if SERIAL_QE |
| help |
| This option provides qe_lib support to UCC slow |
| protocols: UART, BISYNC, QMC |
| |
| config UCC_FAST |
| bool |
| default y if UCC_GETH || QE_TDM |
| help |
| This option provides qe_lib support to UCC fast |
| protocols: HDLC, Ethernet, ATM, transparent |
| |
| config UCC |
| bool |
| default y if UCC_FAST || UCC_SLOW |
| |
| config CPM_TSA |
| tristate "CPM TSA support" |
| depends on OF && HAS_IOMEM |
| depends on CPM1 || (CPM && COMPILE_TEST) |
| help |
| Freescale CPM Time Slot Assigner (TSA) |
| controller. |
| |
| This option enables support for this |
| controller |
| |
| config CPM_QMC |
| tristate "CPM QMC support" |
| depends on OF && HAS_IOMEM |
| depends on CPM1 || (FSL_SOC && CPM && COMPILE_TEST) |
| depends on CPM_TSA |
| help |
| Freescale CPM QUICC Multichannel Controller |
| (QMC) |
| |
| This option enables support for this |
| controller |
| |
| config QE_TDM |
| bool |
| default y if FSL_UCC_HDLC |
| |
| config QE_USB |
| bool |
| depends on QUICC_ENGINE |
| default y if USB_FSL_QE |
| help |
| QE USB Controller support |
