| /* |
| * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| */ |
| /dts-v1/; |
| |
| #include "am33xx.dtsi" |
| #include <dt-bindings/interrupt-controller/irq.h> |
| |
| / { |
| model = "TI AM335x EVM"; |
| compatible = "ti,am335x-evm", "ti,am33xx"; |
| |
| cpus { |
| cpu@0 { |
| cpu0-supply = <&vdd1_reg>; |
| }; |
| }; |
| |
| memory { |
| device_type = "memory"; |
| reg = <0x80000000 0x10000000>; /* 256 MB */ |
| }; |
| |
| vbat: fixedregulator@0 { |
| compatible = "regulator-fixed"; |
| regulator-name = "vbat"; |
| regulator-min-microvolt = <5000000>; |
| regulator-max-microvolt = <5000000>; |
| regulator-boot-on; |
| }; |
| |
| lis3_reg: fixedregulator@1 { |
| compatible = "regulator-fixed"; |
| regulator-name = "lis3_reg"; |
| regulator-boot-on; |
| }; |
| |
| wlan_en_reg: fixedregulator@2 { |
| compatible = "regulator-fixed"; |
| regulator-name = "wlan-en-regulator"; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <1800000>; |
| |
| /* WLAN_EN GPIO for this board - Bank1, pin16 */ |
| gpio = <&gpio1 16 0>; |
| |
| /* WLAN card specific delay */ |
| startup-delay-us = <70000>; |
| enable-active-high; |
| }; |
| |
| matrix_keypad: matrix_keypad@0 { |
| compatible = "gpio-matrix-keypad"; |
| debounce-delay-ms = <5>; |
| col-scan-delay-us = <2>; |
| |
| row-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH /* Bank1, pin25 */ |
| &gpio1 26 GPIO_ACTIVE_HIGH /* Bank1, pin26 */ |
| &gpio1 27 GPIO_ACTIVE_HIGH>; /* Bank1, pin27 */ |
| |
| col-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH /* Bank1, pin21 */ |
| &gpio1 22 GPIO_ACTIVE_HIGH>; /* Bank1, pin22 */ |
| |
| linux,keymap = <0x0000008b /* MENU */ |
| 0x0100009e /* BACK */ |
| 0x02000069 /* LEFT */ |
| 0x0001006a /* RIGHT */ |
| 0x0101001c /* ENTER */ |
| 0x0201006c>; /* DOWN */ |
| }; |
| |
| gpio_keys: volume_keys@0 { |
| compatible = "gpio-keys"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| autorepeat; |
| |
| switch@9 { |
| label = "volume-up"; |
| linux,code = <115>; |
| gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; |
| gpio-key,wakeup; |
| }; |
| |
| switch@10 { |
| label = "volume-down"; |
| linux,code = <114>; |
| gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; |
| gpio-key,wakeup; |
| }; |
| }; |
| |
| backlight { |
| compatible = "pwm-backlight"; |
| pwms = <&ecap0 0 50000 0>; |
| brightness-levels = <0 51 53 56 62 75 101 152 255>; |
| default-brightness-level = <8>; |
| }; |
| |
| panel { |
| compatible = "ti,tilcdc,panel"; |
| status = "okay"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&lcd_pins_s0>; |
| panel-info { |
| ac-bias = <255>; |
| ac-bias-intrpt = <0>; |
| dma-burst-sz = <16>; |
| bpp = <32>; |
| fdd = <0x80>; |
| sync-edge = <0>; |
| sync-ctrl = <1>; |
| raster-order = <0>; |
| fifo-th = <0>; |
| }; |
| |
| display-timings { |
| 800x480p62 { |
| clock-frequency = <30000000>; |
| hactive = <800>; |
| vactive = <480>; |
| hfront-porch = <39>; |
| hback-porch = <39>; |
| hsync-len = <47>; |
| vback-porch = <29>; |
| vfront-porch = <13>; |
| vsync-len = <2>; |
| hsync-active = <1>; |
| vsync-active = <1>; |
| }; |
| }; |
| }; |
| |
| sound { |
| compatible = "ti,da830-evm-audio"; |
| ti,model = "AM335x-EVM"; |
| ti,audio-codec = <&tlv320aic3106>; |
| ti,mcasp-controller = <&mcasp1>; |
| ti,codec-clock-rate = <12000000>; |
| ti,audio-routing = |
| "Headphone Jack", "HPLOUT", |
| "Headphone Jack", "HPROUT", |
| "LINE1L", "Line In", |
| "LINE1R", "Line In"; |
| }; |
| }; |
| |
| &am33xx_pinmux { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0 &clkout2_pin>; |
| |
| matrix_keypad_s0: matrix_keypad_s0 { |
| pinctrl-single,pins = < |
| 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */ |
| 0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a6.gpio1_22 */ |
| 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a9.gpio1_25 */ |
| 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a10.gpio1_26 */ |
| 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a11.gpio1_27 */ |
| >; |
| }; |
| |
| volume_keys_s0: volume_keys_s0 { |
| pinctrl-single,pins = < |
| 0x150 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_sclk.gpio0_2 */ |
| 0x154 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_d0.gpio0_3 */ |
| >; |
| }; |
| |
| i2c0_pins: pinmux_i2c0_pins { |
| pinctrl-single,pins = < |
| 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ |
| 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ |
| >; |
| }; |
| |
| i2c1_pins: pinmux_i2c1_pins { |
| pinctrl-single,pins = < |
| 0x158 (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_d1.i2c1_sda */ |
| 0x15c (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_cs0.i2c1_scl */ |
| >; |
| }; |
| |
| uart0_pins: pinmux_uart0_pins { |
| pinctrl-single,pins = < |
| 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ |
| 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ |
| >; |
| }; |
| |
| uart1_pins: pinmux_uart1_pins { |
| pinctrl-single,pins = < |
| 0x178 (PIN_INPUT | MUX_MODE0) /* uart1_ctsn.uart1_ctsn */ |
| 0x17C (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn.uart1_rtsn */ |
| 0x180 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */ |
| 0x184 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */ |
| >; |
| }; |
| |
| clkout2_pin: pinmux_clkout2_pin { |
| pinctrl-single,pins = < |
| 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ |
| >; |
| }; |
| |
| nandflash_pins_s0: nandflash_pins_s0 { |
| pinctrl-single,pins = < |
| 0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ |
| 0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ |
| 0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ |
| 0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ |
| 0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ |
| 0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ |
| 0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ |
| 0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ |
| 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ |
| 0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */ |
| 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ |
| 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ |
| 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ |
| 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ |
| 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ |
| >; |
| }; |
| |
| ecap0_pins: backlight_pins { |
| pinctrl-single,pins = < |
| 0x164 0x0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */ |
| >; |
| }; |
| |
| cpsw_default: cpsw_default { |
| pinctrl-single,pins = < |
| /* Slave 1 */ |
| 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ |
| 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ |
| 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ |
| 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ |
| 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ |
| 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ |
| 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ |
| 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ |
| 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */ |
| 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */ |
| 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ |
| 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ |
| >; |
| }; |
| |
| cpsw_sleep: cpsw_sleep { |
| pinctrl-single,pins = < |
| /* Slave 1 reset value */ |
| 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| >; |
| }; |
| |
| davinci_mdio_default: davinci_mdio_default { |
| pinctrl-single,pins = < |
| /* MDIO */ |
| 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ |
| 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ |
| >; |
| }; |
| |
| davinci_mdio_sleep: davinci_mdio_sleep { |
| pinctrl-single,pins = < |
| /* MDIO reset value */ |
| 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| >; |
| }; |
| |
| mmc1_pins: pinmux_mmc1_pins { |
| pinctrl-single,pins = < |
| 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ |
| >; |
| }; |
| |
| mmc3_pins: pinmux_mmc3_pins { |
| pinctrl-single,pins = < |
| 0x44 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a1.mmc2_dat0, INPUT_PULLUP | MODE3 */ |
| 0x48 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a2.mmc2_dat1, INPUT_PULLUP | MODE3 */ |
| 0x4C (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a3.mmc2_dat2, INPUT_PULLUP | MODE3 */ |
| 0x78 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ben1.mmc2_dat3, INPUT_PULLUP | MODE3 */ |
| 0x88 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd, INPUT_PULLUP | MODE3 */ |
| 0x8C (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc2_clk, INPUT_PULLUP | MODE3 */ |
| >; |
| }; |
| |
| wlan_pins: pinmux_wlan_pins { |
| pinctrl-single,pins = < |
| 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.gpio1_16 */ |
| 0x19C (PIN_INPUT | MUX_MODE7) /* mcasp0_ahclkr.gpio3_17 */ |
| 0x1AC (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mcasp0_ahclkx.gpio3_21 */ |
| >; |
| }; |
| |
| lcd_pins_s0: lcd_pins_s0 { |
| pinctrl-single,pins = < |
| 0x20 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad8.lcd_data23 */ |
| 0x24 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad9.lcd_data22 */ |
| 0x28 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad10.lcd_data21 */ |
| 0x2c (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad11.lcd_data20 */ |
| 0x30 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad12.lcd_data19 */ |
| 0x34 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad13.lcd_data18 */ |
| 0x38 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad14.lcd_data17 */ |
| 0x3c (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad15.lcd_data16 */ |
| 0xa0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */ |
| 0xa4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */ |
| 0xa8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */ |
| 0xac (PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */ |
| 0xb0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */ |
| 0xb4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */ |
| 0xb8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */ |
| 0xbc (PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */ |
| 0xc0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */ |
| 0xc4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */ |
| 0xc8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */ |
| 0xcc (PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */ |
| 0xd0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */ |
| 0xd4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */ |
| 0xd8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */ |
| 0xdc (PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */ |
| 0xe0 (PIN_OUTPUT | MUX_MODE0) /* lcd_vsync.lcd_vsync */ |
| 0xe4 (PIN_OUTPUT | MUX_MODE0) /* lcd_hsync.lcd_hsync */ |
| 0xe8 (PIN_OUTPUT | MUX_MODE0) /* lcd_pclk.lcd_pclk */ |
| 0xec (PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */ |
| >; |
| }; |
| |
| am335x_evm_audio_pins: am335x_evm_audio_pins { |
| pinctrl-single,pins = < |
| 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */ |
| 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */ |
| 0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */ |
| 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ |
| >; |
| }; |
| |
| dcan1_pins_default: dcan1_pins_default { |
| pinctrl-single,pins = < |
| 0x168 (PIN_OUTPUT | MUX_MODE2) /* uart0_ctsn.d_can1_tx */ |
| 0x16c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* uart0_rtsn.d_can1_rx */ |
| >; |
| }; |
| }; |
| |
| &uart0 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&uart0_pins>; |
| |
| status = "okay"; |
| }; |
| |
| &uart1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&uart1_pins>; |
| |
| status = "okay"; |
| }; |
| |
| &i2c0 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&i2c0_pins>; |
| |
| status = "okay"; |
| clock-frequency = <400000>; |
| |
| tps: tps@2d { |
| reg = <0x2d>; |
| }; |
| }; |
| |
| &usb { |
| status = "okay"; |
| }; |
| |
| &usb_ctrl_mod { |
| status = "okay"; |
| }; |
| |
| &usb0_phy { |
| status = "okay"; |
| }; |
| |
| &usb1_phy { |
| status = "okay"; |
| }; |
| |
| &usb0 { |
| status = "okay"; |
| }; |
| |
| &usb1 { |
| status = "okay"; |
| dr_mode = "host"; |
| }; |
| |
| &cppi41dma { |
| status = "okay"; |
| }; |
| |
| &i2c1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&i2c1_pins>; |
| |
| status = "okay"; |
| clock-frequency = <100000>; |
| |
| lis331dlh: lis331dlh@18 { |
| compatible = "st,lis331dlh", "st,lis3lv02d"; |
| reg = <0x18>; |
| Vdd-supply = <&lis3_reg>; |
| Vdd_IO-supply = <&lis3_reg>; |
| |
| st,click-single-x; |
| st,click-single-y; |
| st,click-single-z; |
| st,click-thresh-x = <10>; |
| st,click-thresh-y = <10>; |
| st,click-thresh-z = <10>; |
| st,irq1-click; |
| st,irq2-click; |
| st,wakeup-x-lo; |
| st,wakeup-x-hi; |
| st,wakeup-y-lo; |
| st,wakeup-y-hi; |
| st,wakeup-z-lo; |
| st,wakeup-z-hi; |
| st,min-limit-x = <120>; |
| st,min-limit-y = <120>; |
| st,min-limit-z = <140>; |
| st,max-limit-x = <550>; |
| st,max-limit-y = <550>; |
| st,max-limit-z = <750>; |
| }; |
| |
| tsl2550: tsl2550@39 { |
| compatible = "taos,tsl2550"; |
| reg = <0x39>; |
| }; |
| |
| tmp275: tmp275@48 { |
| compatible = "ti,tmp275"; |
| reg = <0x48>; |
| }; |
| |
| tlv320aic3106: tlv320aic3106@1b { |
| compatible = "ti,tlv320aic3106"; |
| reg = <0x1b>; |
| status = "okay"; |
| |
| /* Regulators */ |
| AVDD-supply = <&vaux2_reg>; |
| IOVDD-supply = <&vaux2_reg>; |
| DRVDD-supply = <&vaux2_reg>; |
| DVDD-supply = <&vbat>; |
| }; |
| }; |
| |
| &lcdc { |
| status = "okay"; |
| }; |
| |
| &elm { |
| status = "okay"; |
| }; |
| |
| &epwmss0 { |
| status = "okay"; |
| |
| ecap0: ecap@48300100 { |
| status = "okay"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&ecap0_pins>; |
| }; |
| }; |
| |
| &gpmc { |
| status = "okay"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&nandflash_pins_s0>; |
| ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */ |
| nand@0,0 { |
| reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ |
| ti,nand-ecc-opt = "bch8"; |
| ti,elm-id = <&elm>; |
| nand-bus-width = <8>; |
| gpmc,device-width = <1>; |
| gpmc,sync-clk-ps = <0>; |
| gpmc,cs-on-ns = <0>; |
| gpmc,cs-rd-off-ns = <44>; |
| gpmc,cs-wr-off-ns = <44>; |
| gpmc,adv-on-ns = <6>; |
| gpmc,adv-rd-off-ns = <34>; |
| gpmc,adv-wr-off-ns = <44>; |
| gpmc,we-on-ns = <0>; |
| gpmc,we-off-ns = <40>; |
| gpmc,oe-on-ns = <0>; |
| gpmc,oe-off-ns = <54>; |
| gpmc,access-ns = <64>; |
| gpmc,rd-cycle-ns = <82>; |
| gpmc,wr-cycle-ns = <82>; |
| gpmc,wait-on-read = "true"; |
| gpmc,wait-on-write = "true"; |
| gpmc,bus-turnaround-ns = <0>; |
| gpmc,cycle2cycle-delay-ns = <0>; |
| gpmc,clk-activation-ns = <0>; |
| gpmc,wait-monitoring-ns = <0>; |
| gpmc,wr-access-ns = <40>; |
| gpmc,wr-data-mux-bus-ns = <0>; |
| /* MTD partition table */ |
| /* All SPL-* partitions are sized to minimal length |
| * which can be independently programmable. For |
| * NAND flash this is equal to size of erase-block */ |
| #address-cells = <1>; |
| #size-cells = <1>; |
| partition@0 { |
| label = "NAND.SPL"; |
| reg = <0x00000000 0x000020000>; |
| }; |
| partition@1 { |
| label = "NAND.SPL.backup1"; |
| reg = <0x00020000 0x00020000>; |
| }; |
| partition@2 { |
| label = "NAND.SPL.backup2"; |
| reg = <0x00040000 0x00020000>; |
| }; |
| partition@3 { |
| label = "NAND.SPL.backup3"; |
| reg = <0x00060000 0x00020000>; |
| }; |
| partition@4 { |
| label = "NAND.u-boot-spl-os"; |
| reg = <0x00080000 0x00040000>; |
| }; |
| partition@5 { |
| label = "NAND.u-boot"; |
| reg = <0x000C0000 0x00100000>; |
| }; |
| partition@6 { |
| label = "NAND.u-boot-env"; |
| reg = <0x001C0000 0x00020000>; |
| }; |
| partition@7 { |
| label = "NAND.u-boot-env.backup1"; |
| reg = <0x001E0000 0x00020000>; |
| }; |
| partition@8 { |
| label = "NAND.kernel"; |
| reg = <0x00200000 0x00800000>; |
| }; |
| partition@9 { |
| label = "NAND.file-system"; |
| reg = <0x00A00000 0x0F600000>; |
| }; |
| }; |
| }; |
| |
| #include "tps65910.dtsi" |
| |
| &mcasp1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&am335x_evm_audio_pins>; |
| |
| status = "okay"; |
| |
| op-mode = <0>; /* MCASP_IIS_MODE */ |
| tdm-slots = <2>; |
| /* 4 serializers */ |
| serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ |
| 0 0 1 2 |
| >; |
| tx-num-evt = <32>; |
| rx-num-evt = <32>; |
| }; |
| |
| &tps { |
| vcc1-supply = <&vbat>; |
| vcc2-supply = <&vbat>; |
| vcc3-supply = <&vbat>; |
| vcc4-supply = <&vbat>; |
| vcc5-supply = <&vbat>; |
| vcc6-supply = <&vbat>; |
| vcc7-supply = <&vbat>; |
| vccio-supply = <&vbat>; |
| |
| regulators { |
| vrtc_reg: regulator@0 { |
| regulator-always-on; |
| }; |
| |
| vio_reg: regulator@1 { |
| regulator-always-on; |
| }; |
| |
| vdd1_reg: regulator@2 { |
| /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ |
| regulator-name = "vdd_mpu"; |
| regulator-min-microvolt = <912500>; |
| regulator-max-microvolt = <1312500>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| vdd2_reg: regulator@3 { |
| /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ |
| regulator-name = "vdd_core"; |
| regulator-min-microvolt = <912500>; |
| regulator-max-microvolt = <1150000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| vdd3_reg: regulator@4 { |
| regulator-always-on; |
| }; |
| |
| vdig1_reg: regulator@5 { |
| regulator-always-on; |
| }; |
| |
| vdig2_reg: regulator@6 { |
| regulator-always-on; |
| }; |
| |
| vpll_reg: regulator@7 { |
| regulator-always-on; |
| }; |
| |
| vdac_reg: regulator@8 { |
| regulator-always-on; |
| }; |
| |
| vaux1_reg: regulator@9 { |
| regulator-always-on; |
| }; |
| |
| vaux2_reg: regulator@10 { |
| regulator-always-on; |
| }; |
| |
| vaux33_reg: regulator@11 { |
| regulator-always-on; |
| }; |
| |
| vmmc_reg: regulator@12 { |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| }; |
| }; |
| }; |
| |
| &mac { |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&cpsw_default>; |
| pinctrl-1 = <&cpsw_sleep>; |
| status = "okay"; |
| }; |
| |
| &davinci_mdio { |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&davinci_mdio_default>; |
| pinctrl-1 = <&davinci_mdio_sleep>; |
| status = "okay"; |
| }; |
| |
| &cpsw_emac0 { |
| phy_id = <&davinci_mdio>, <0>; |
| phy-mode = "rgmii-txid"; |
| }; |
| |
| &cpsw_emac1 { |
| phy_id = <&davinci_mdio>, <1>; |
| phy-mode = "rgmii-txid"; |
| }; |
| |
| &tscadc { |
| status = "okay"; |
| tsc { |
| ti,wires = <4>; |
| ti,x-plate-resistance = <200>; |
| ti,coordinate-readouts = <5>; |
| ti,wire-config = <0x00 0x11 0x22 0x33>; |
| ti,charge-delay = <0x400>; |
| }; |
| |
| adc { |
| ti,adc-channels = <4 5 6 7>; |
| }; |
| }; |
| |
| &mmc1 { |
| status = "okay"; |
| vmmc-supply = <&vmmc_reg>; |
| bus-width = <4>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&mmc1_pins>; |
| cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; |
| }; |
| |
| &mmc3 { |
| /* these are on the crossbar and are outlined in the |
| xbar-event-map element */ |
| dmas = <&edma 12 |
| &edma 13>; |
| dma-names = "tx", "rx"; |
| status = "okay"; |
| vmmc-supply = <&wlan_en_reg>; |
| bus-width = <4>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&mmc3_pins &wlan_pins>; |
| ti,non-removable; |
| ti,needs-special-hs-handling; |
| cap-power-off-card; |
| keep-power-in-suspend; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| wlcore: wlcore@0 { |
| compatible = "ti,wl1835"; |
| reg = <2>; |
| interrupt-parent = <&gpio3>; |
| interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| }; |
| |
| &edma { |
| ti,edma-xbar-event-map = /bits/ 16 <1 12 |
| 2 13>; |
| }; |
| |
| &sham { |
| status = "okay"; |
| }; |
| |
| &aes { |
| status = "okay"; |
| }; |
| |
| &dcan1 { |
| status = "disabled"; /* Enable only if Profile 1 is selected */ |
| pinctrl-names = "default"; |
| pinctrl-0 = <&dcan1_pins_default>; |
| }; |
