| // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| /* |
| * Device Tree Source for the RZ/G2UL SoC |
| * |
| * Copyright (C) 2022 Renesas Electronics Corp. |
| */ |
| |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| |
| #define SOC_PERIPHERAL_IRQ(nr) GIC_SPI nr |
| |
| #include "r9a07g043.dtsi" |
| |
| / { |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu0: cpu@0 { |
| compatible = "arm,cortex-a55"; |
| reg = <0>; |
| device_type = "cpu"; |
| #cooling-cells = <2>; |
| next-level-cache = <&L3_CA55>; |
| enable-method = "psci"; |
| clocks = <&cpg CPG_CORE R9A07G043_CLK_I>; |
| operating-points-v2 = <&cluster0_opp>; |
| }; |
| |
| L3_CA55: cache-controller-0 { |
| compatible = "cache"; |
| cache-unified; |
| cache-size = <0x40000>; |
| cache-level = <3>; |
| }; |
| }; |
| |
| psci { |
| compatible = "arm,psci-1.0", "arm,psci-0.2"; |
| method = "smc"; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, |
| <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, |
| <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, |
| <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; |
| }; |
| }; |
| |
| &soc { |
| interrupt-parent = <&gic>; |
| |
| gic: interrupt-controller@11900000 { |
| compatible = "arm,gic-v3"; |
| #interrupt-cells = <3>; |
| #address-cells = <0>; |
| interrupt-controller; |
| reg = <0x0 0x11900000 0 0x40000>, |
| <0x0 0x11940000 0 0x60000>; |
| interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; |
| }; |
| }; |
| |
| &sysc { |
| interrupts = <SOC_PERIPHERAL_IRQ(42) IRQ_TYPE_LEVEL_HIGH>, |
| <SOC_PERIPHERAL_IRQ(43) IRQ_TYPE_LEVEL_HIGH>, |
| <SOC_PERIPHERAL_IRQ(44) IRQ_TYPE_LEVEL_HIGH>, |
| <SOC_PERIPHERAL_IRQ(45) IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "lpm_int", "ca55stbydone_int", |
| "cm33stbyr_int", "ca55_deny"; |
| }; |