| // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| /* |
| * Copyright 2020 NXP |
| */ |
| |
| /dts-v1/; |
| |
| #include <dt-bindings/phy/phy-imx8-pcie.h> |
| #include <dt-bindings/usb/pd.h> |
| #include "imx8mm.dtsi" |
| |
| / { |
| chosen { |
| stdout-path = &uart2; |
| }; |
| |
| memory@40000000 { |
| device_type = "memory"; |
| reg = <0x0 0x40000000 0 0x80000000>; |
| }; |
| |
| hdmi-connector { |
| compatible = "hdmi-connector"; |
| label = "hdmi"; |
| type = "a"; |
| |
| port { |
| hdmi_connector_in: endpoint { |
| remote-endpoint = <&adv7535_out>; |
| }; |
| }; |
| }; |
| |
| leds { |
| compatible = "gpio-leds"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_gpio_led>; |
| |
| status { |
| label = "status"; |
| gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; |
| default-state = "on"; |
| }; |
| }; |
| |
| pcie0_refclk: pcie0-refclk { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <100000000>; |
| }; |
| |
| reg_pcie0: regulator-pcie { |
| compatible = "regulator-fixed"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_pcie0_reg>; |
| regulator-name = "MPCIE_3V3"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| }; |
| |
| reg_usdhc2_vmmc: regulator-usdhc2 { |
| compatible = "regulator-fixed"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; |
| regulator-name = "VSD_3V3"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; |
| off-on-delay-us = <20000>; |
| enable-active-high; |
| }; |
| |
| reg_vddext_3v3: regulator-vddext-3v3 { |
| compatible = "regulator-fixed"; |
| regulator-name = "VDDEXT_3V3"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| }; |
| |
| backlight: backlight { |
| compatible = "pwm-backlight"; |
| pwms = <&pwm1 0 5000000 0>; |
| brightness-levels = <0 255>; |
| num-interpolated-steps = <255>; |
| default-brightness-level = <250>; |
| }; |
| |
| ir-receiver { |
| compatible = "gpio-ir-receiver"; |
| gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_ir>; |
| linux,autosuspend-period = <125>; |
| }; |
| |
| audio_codec_bt_sco: audio-codec-bt-sco { |
| compatible = "linux,bt-sco"; |
| #sound-dai-cells = <1>; |
| }; |
| |
| wm8524: audio-codec { |
| #sound-dai-cells = <0>; |
| compatible = "wlf,wm8524"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_gpio_wlf>; |
| wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>; |
| }; |
| |
| sound-bt-sco { |
| compatible = "simple-audio-card"; |
| simple-audio-card,name = "bt-sco-audio"; |
| simple-audio-card,format = "dsp_a"; |
| simple-audio-card,bitclock-inversion; |
| simple-audio-card,frame-master = <&btcpu>; |
| simple-audio-card,bitclock-master = <&btcpu>; |
| |
| btcpu: simple-audio-card,cpu { |
| sound-dai = <&sai2>; |
| dai-tdm-slot-num = <2>; |
| dai-tdm-slot-width = <16>; |
| }; |
| |
| simple-audio-card,codec { |
| sound-dai = <&audio_codec_bt_sco 1>; |
| }; |
| }; |
| |
| sound-wm8524 { |
| compatible = "simple-audio-card"; |
| simple-audio-card,name = "wm8524-audio"; |
| simple-audio-card,format = "i2s"; |
| simple-audio-card,frame-master = <&cpudai>; |
| simple-audio-card,bitclock-master = <&cpudai>; |
| simple-audio-card,widgets = |
| "Line", "Left Line Out Jack", |
| "Line", "Right Line Out Jack"; |
| simple-audio-card,routing = |
| "Left Line Out Jack", "LINEVOUTL", |
| "Right Line Out Jack", "LINEVOUTR"; |
| |
| cpudai: simple-audio-card,cpu { |
| sound-dai = <&sai3>; |
| dai-tdm-slot-num = <2>; |
| dai-tdm-slot-width = <32>; |
| }; |
| |
| simple-audio-card,codec { |
| sound-dai = <&wm8524>; |
| clocks = <&clk IMX8MM_CLK_SAI3_ROOT>; |
| }; |
| }; |
| }; |
| |
| &A53_0 { |
| cpu-supply = <&buck2_reg>; |
| }; |
| |
| &A53_1 { |
| cpu-supply = <&buck2_reg>; |
| }; |
| |
| &A53_2 { |
| cpu-supply = <&buck2_reg>; |
| }; |
| |
| &A53_3 { |
| cpu-supply = <&buck2_reg>; |
| }; |
| |
| &fec1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_fec1>; |
| phy-mode = "rgmii-id"; |
| phy-handle = <ðphy0>; |
| fsl,magic-packet; |
| status = "okay"; |
| |
| mdio { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| ethphy0: ethernet-phy@0 { |
| compatible = "ethernet-phy-ieee802.3-c22"; |
| reg = <0>; |
| reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; |
| reset-assert-us = <10000>; |
| qca,disable-smarteee; |
| vddio-supply = <&vddio>; |
| |
| vddio: vddio-regulator { |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <1800000>; |
| }; |
| }; |
| }; |
| }; |
| |
| &i2c1 { |
| clock-frequency = <400000>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_i2c1>; |
| status = "okay"; |
| |
| pmic@4b { |
| compatible = "rohm,bd71847"; |
| reg = <0x4b>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_pmic>; |
| interrupt-parent = <&gpio1>; |
| interrupts = <3 IRQ_TYPE_LEVEL_LOW>; |
| rohm,reset-snvs-powered; |
| |
| #clock-cells = <0>; |
| clocks = <&osc_32k>; |
| clock-output-names = "clk-32k-out"; |
| |
| regulators { |
| buck1_reg: BUCK1 { |
| regulator-name = "buck1"; |
| regulator-min-microvolt = <700000>; |
| regulator-max-microvolt = <1300000>; |
| regulator-boot-on; |
| regulator-always-on; |
| regulator-ramp-delay = <1250>; |
| }; |
| |
| buck2_reg: BUCK2 { |
| regulator-name = "buck2"; |
| regulator-min-microvolt = <700000>; |
| regulator-max-microvolt = <1300000>; |
| regulator-boot-on; |
| regulator-always-on; |
| regulator-ramp-delay = <1250>; |
| rohm,dvs-run-voltage = <1000000>; |
| rohm,dvs-idle-voltage = <900000>; |
| }; |
| |
| buck3_reg: BUCK3 { |
| // BUCK5 in datasheet |
| regulator-name = "buck3"; |
| regulator-min-microvolt = <700000>; |
| regulator-max-microvolt = <1350000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| buck4_reg: BUCK4 { |
| // BUCK6 in datasheet |
| regulator-name = "buck4"; |
| regulator-min-microvolt = <3000000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| buck5_reg: BUCK5 { |
| // BUCK7 in datasheet |
| regulator-name = "buck5"; |
| regulator-min-microvolt = <1605000>; |
| regulator-max-microvolt = <1995000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| buck6_reg: BUCK6 { |
| // BUCK8 in datasheet |
| regulator-name = "buck6"; |
| regulator-min-microvolt = <800000>; |
| regulator-max-microvolt = <1400000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| ldo1_reg: LDO1 { |
| regulator-name = "ldo1"; |
| regulator-min-microvolt = <1600000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| ldo2_reg: LDO2 { |
| regulator-name = "ldo2"; |
| regulator-min-microvolt = <800000>; |
| regulator-max-microvolt = <900000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| ldo3_reg: LDO3 { |
| regulator-name = "ldo3"; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| ldo4_reg: LDO4 { |
| regulator-name = "ldo4"; |
| regulator-min-microvolt = <900000>; |
| regulator-max-microvolt = <1800000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| ldo6_reg: LDO6 { |
| regulator-name = "ldo6"; |
| regulator-min-microvolt = <900000>; |
| regulator-max-microvolt = <1800000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| }; |
| }; |
| }; |
| |
| &i2c2 { |
| clock-frequency = <400000>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_i2c2>; |
| status = "okay"; |
| |
| hdmi@3d { |
| compatible = "adi,adv7535"; |
| reg = <0x3d>; |
| interrupt-parent = <&gpio1>; |
| interrupts = <9 IRQ_TYPE_EDGE_FALLING>; |
| adi,dsi-lanes = <4>; |
| avdd-supply = <&buck5_reg>; |
| dvdd-supply = <&buck5_reg>; |
| pvdd-supply = <&buck5_reg>; |
| a2vdd-supply = <&buck5_reg>; |
| v3p3-supply = <®_vddext_3v3>; |
| v1p2-supply = <&buck5_reg>; |
| |
| ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| reg = <0>; |
| |
| adv7535_in: endpoint { |
| remote-endpoint = <&dsi_out>; |
| }; |
| }; |
| |
| port@1 { |
| reg = <1>; |
| |
| adv7535_out: endpoint { |
| remote-endpoint = <&hdmi_connector_in>; |
| }; |
| }; |
| |
| }; |
| }; |
| |
| ptn5110: tcpc@50 { |
| compatible = "nxp,ptn5110"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_typec1>; |
| reg = <0x50>; |
| interrupt-parent = <&gpio2>; |
| interrupts = <11 8>; |
| status = "okay"; |
| |
| typec1_con: connector { |
| compatible = "usb-c-connector"; |
| label = "USB-C"; |
| power-role = "dual"; |
| data-role = "dual"; |
| try-power-role = "sink"; |
| source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; |
| sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) |
| PDO_VAR(5000, 20000, 3000)>; |
| op-sink-microwatt = <15000000>; |
| self-powered; |
| |
| port { |
| typec1_dr_sw: endpoint { |
| remote-endpoint = <&usb1_drd_sw>; |
| }; |
| }; |
| }; |
| }; |
| }; |
| |
| |
| &csi { |
| status = "okay"; |
| }; |
| |
| &i2c3 { |
| clock-frequency = <400000>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_i2c3>; |
| status = "okay"; |
| |
| pca6416: gpio@20 { |
| compatible = "nxp,pca6416"; |
| reg = <0x20>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| vcc-supply = <&buck4_reg>; |
| }; |
| |
| camera@3c { |
| compatible = "ovti,ov5640"; |
| reg = <0x3c>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_camera>; |
| clocks = <&clk IMX8MM_CLK_CLKO1>; |
| clock-names = "xclk"; |
| assigned-clocks = <&clk IMX8MM_CLK_CLKO1>; |
| assigned-clock-parents = <&clk IMX8MM_CLK_24M>; |
| assigned-clock-rates = <24000000>; |
| powerdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; |
| reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; |
| |
| port { |
| ov5640_to_mipi_csi2: endpoint { |
| remote-endpoint = <&imx8mm_mipi_csi_in>; |
| clock-lanes = <0>; |
| data-lanes = <1 2>; |
| }; |
| }; |
| }; |
| }; |
| |
| &lcdif { |
| status = "okay"; |
| }; |
| |
| &mipi_csi { |
| status = "okay"; |
| |
| ports { |
| port@0 { |
| imx8mm_mipi_csi_in: endpoint { |
| remote-endpoint = <&ov5640_to_mipi_csi2>; |
| data-lanes = <1 2>; |
| }; |
| }; |
| }; |
| }; |
| |
| &mipi_dsi { |
| samsung,esc-clock-frequency = <10000000>; |
| status = "okay"; |
| |
| ports { |
| port@1 { |
| reg = <1>; |
| |
| dsi_out: endpoint { |
| remote-endpoint = <&adv7535_in>; |
| data-lanes = <1 2 3 4>; |
| }; |
| }; |
| }; |
| }; |
| |
| &pcie_phy { |
| fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; |
| fsl,tx-deemph-gen1 = <0x2d>; |
| fsl,tx-deemph-gen2 = <0xf>; |
| clocks = <&pcie0_refclk>; |
| status = "okay"; |
| }; |
| |
| &pcie0 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_pcie0>; |
| reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>; |
| clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>, |
| <&clk IMX8MM_CLK_PCIE1_AUX>; |
| assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, |
| <&clk IMX8MM_CLK_PCIE1_CTRL>; |
| assigned-clock-rates = <10000000>, <250000000>; |
| assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, |
| <&clk IMX8MM_SYS_PLL2_250M>; |
| vpcie-supply = <®_pcie0>; |
| status = "okay"; |
| }; |
| |
| &sai2 { |
| #sound-dai-cells = <0>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_sai2>; |
| assigned-clocks = <&clk IMX8MM_CLK_SAI2>; |
| assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; |
| assigned-clock-rates = <24576000>; |
| status = "okay"; |
| }; |
| |
| &sai3 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_sai3>; |
| assigned-clocks = <&clk IMX8MM_CLK_SAI3>; |
| assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; |
| assigned-clock-rates = <24576000>; |
| status = "okay"; |
| }; |
| |
| &snvs_pwrkey { |
| status = "okay"; |
| }; |
| |
| &uart2 { /* console */ |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart2>; |
| status = "okay"; |
| }; |
| |
| &usbphynop1 { |
| wakeup-source; |
| }; |
| |
| &usbotg1 { |
| dr_mode = "otg"; |
| hnp-disable; |
| srp-disable; |
| adp-disable; |
| usb-role-switch; |
| disable-over-current; |
| samsung,picophy-pre-emp-curr-control = <3>; |
| samsung,picophy-dc-vol-level-adjust = <7>; |
| status = "okay"; |
| |
| port { |
| usb1_drd_sw: endpoint { |
| remote-endpoint = <&typec1_dr_sw>; |
| }; |
| }; |
| }; |
| |
| &usdhc2 { |
| assigned-clocks = <&clk IMX8MM_CLK_USDHC2>; |
| assigned-clock-rates = <200000000>; |
| pinctrl-names = "default", "state_100mhz", "state_200mhz"; |
| pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; |
| pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; |
| pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; |
| cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; |
| bus-width = <4>; |
| vmmc-supply = <®_usdhc2_vmmc>; |
| status = "okay"; |
| }; |
| |
| &wdog1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_wdog>; |
| fsl,ext-reset-output; |
| status = "okay"; |
| }; |
| |
| &pwm1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_backlight>; |
| status = "okay"; |
| }; |
| |
| &iomuxc { |
| pinctrl_fec1: fec1grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 |
| MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 |
| MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f |
| MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f |
| MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f |
| MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f |
| MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 |
| MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 |
| MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 |
| MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 |
| MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f |
| MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 |
| MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 |
| MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f |
| MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 |
| >; |
| }; |
| |
| pinctrl_gpio_led: gpioledgrp { |
| fsl,pins = < |
| MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 |
| >; |
| }; |
| |
| pinctrl_ir: irgrp { |
| fsl,pins = < |
| MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x4f |
| >; |
| }; |
| |
| pinctrl_gpio_wlf: gpiowlfgrp { |
| fsl,pins = < |
| MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0xd6 |
| >; |
| }; |
| |
| pinctrl_i2c1: i2c1grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 |
| MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 |
| >; |
| }; |
| |
| pinctrl_i2c2: i2c2grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 |
| MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 |
| >; |
| }; |
| |
| pinctrl_i2c3: i2c3grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 |
| MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 |
| >; |
| }; |
| |
| pinctrl_pcie0: pcie0grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x61 |
| MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x41 |
| >; |
| }; |
| |
| pinctrl_pcie0_reg: pcie0reggrp { |
| fsl,pins = < |
| MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x41 |
| >; |
| }; |
| |
| pinctrl_pmic: pmicirqgrp { |
| fsl,pins = < |
| MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 |
| >; |
| }; |
| |
| pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { |
| fsl,pins = < |
| MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 |
| >; |
| }; |
| |
| pinctrl_sai2: sai2grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 |
| MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 |
| MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 |
| MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 |
| >; |
| }; |
| |
| pinctrl_sai3: sai3grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 |
| MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 |
| MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 |
| MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 |
| >; |
| }; |
| |
| pinctrl_typec1: typec1grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159 |
| >; |
| }; |
| |
| pinctrl_uart2: uart2grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 |
| MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 |
| >; |
| }; |
| |
| pinctrl_usdhc2_gpio: usdhc2grpgpiogrp { |
| fsl,pins = < |
| MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4 |
| >; |
| }; |
| |
| pinctrl_usdhc2: usdhc2grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 |
| MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 |
| MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 |
| MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 |
| MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 |
| MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 |
| MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 |
| >; |
| }; |
| |
| pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { |
| fsl,pins = < |
| MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 |
| MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 |
| MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 |
| MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 |
| MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 |
| MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 |
| MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 |
| >; |
| }; |
| |
| pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { |
| fsl,pins = < |
| MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 |
| MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 |
| MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 |
| MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 |
| MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 |
| MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 |
| MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 |
| >; |
| }; |
| |
| pinctrl_wdog: wdoggrp { |
| fsl,pins = < |
| MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166 |
| >; |
| }; |
| |
| pinctrl_backlight: backlightgrp { |
| fsl,pins = < |
| MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x06 |
| >; |
| }; |
| |
| pinctrl_camera: cameragrp { |
| fsl,pins = < |
| MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 |
| MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 |
| MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59 |
| >; |
| }; |
| }; |
